Sunky Blog

PTX ISA 9.4：10. 特殊寄存器

Mon, 28 Sep 2026 00:00:00 GMT

10.1. 特殊寄存器：%tid

// legacy code accessing 16-bit components of %tid mov.u16 %rh,%tid.x; cvt.u32.u16 %r2,%tid.z; // zero-extend tid.z to %r2

10.2. 特殊寄存器：%ntid

mov.u16 %rh,%ntid.x; // legacy code

10.3. 特殊寄存器：%laneid

10.4. 特殊寄存器：%warpid

10.5. 特殊寄存器：%nwarpid

10.6. 特殊寄存器：%ctaid

10.7. 特殊寄存器：%nctaid

10.8. 特殊寄存器：%smid

10.9. 特殊寄存器：%nsmid

10.10. 特殊寄存器：%gridid

10.11. 特殊寄存器：%is_explicit_cluster

mov.pred p, %is_explicit_cluster;

10.12. 特殊寄存器：%clusterid

mov.u32 %r0, %clusterid.x; mov.u32 %r1, %clusterid.z; mov.v4.u32 %rx, %clusterid;

10.13. 特殊寄存器：%nclusterid

mov.u32 %r0, %nclusterid.x; mov.u32 %r1, %nclusterid.z; mov.v4.u32 %rx, %nclusterid;

10.14. 特殊寄存器：%cluster_ctaid

mov.u32 %r0, %cluster_ctaid.x; mov.u32 %r1, %cluster_ctaid.z; mov.v4.u32 %rx, %cluster_ctaid;

10.15. 特殊寄存器：%cluster_nctaid

mov.u32 %r0, %cluster_nctaid.x; mov.u32 %r1, %cluster_nctaid.z; mov.v4.u32 %rx, %cluster_nctaid;

10.16. 特殊寄存器：%cluster_ctarank

mov.u32 %r, %cluster_ctarank;

10.17. 特殊寄存器：%cluster_nctarank

mov.u32 %r, %cluster_nctarank;

10.18. 特殊寄存器：%lanemask_eq

10.19. 特殊寄存器：%lanemask_le

10.20. 特殊寄存器：%lanemask_lt

10.21. 特殊寄存器：%lanemask_ge

10.22. 特殊寄存器：%lanemask_gt

10.23. 特殊寄存器：%clock , %clock_hi

10.24. 特殊寄存器：%clock64

10.25. 特殊寄存器：%pm0 … %pm7

10.26. 特殊寄存器：%pm0_64 … %pm7_64

10.27. 特殊寄存器：%envreg<32>

10.28. 特殊寄存器：%globaltimer , %globaltimer_lo , %globaltimer_hi

10.29. 特殊寄存器：%reserved_smem_offset_begin , %reserved_smem_offset_end , %reserved_smem_offset_cap , %reserved_smem_offset_<2>

mov.b32 %reg_begin, %reserved_smem_offset_begin; mov.b32 %reg_end, %reserved_smem_offset_end; mov.b32 %reg_cap, %reserved_smem_offset_cap; mov.b32 %reg_offset0, %reserved_smem_offset_0; mov.b32 %reg_offset1, %reserved_smem_offset_1;

10.30. 特殊寄存器：%total_smem_size

10.31. 特殊寄存器：%aggr_smem_size

10.32. 特殊寄存器：%dynamic_smem_size

10.33. 特殊寄存器：%current_graph_exec

10.34. 特殊寄存器：%perctamemoryoffset

10.35. 特殊寄存器：%perctamemorysize

PTX ISA 9.4：11. 指示符

Mon, 28 Sep 2026 00:00:00 GMT

11.1. PTX 模块指示符

11.1.1. PTX 模块指示符：.version

11.1.2. PTX 模块指示符：.target

11.1.3. PTX 模块指示符：.address_size

// example of directive placement within a module .version 2.3 .target sm_20 .address_size 64 ... .entry foo () { ... }

11.2. 指定 Kernel 入口点与函数

11.2.1. Kernel 与函数指示符：.entry

.entry prefix_sum ( .param .align 4 .s32 pitch[8000] ) { .reg .s32 %t; ld.param::entry.s32 %t, [pitch]; ... }

11.2.2. Kernel 与函数指示符：.func

... use N, dbl; other code;

mov.b32 rval,result; ret; }

... call (fooval), foo, (val0, val1); // return value in fooval ...

.func foo (.reg .b32 N, .reg .f64 dbl) .noreturn { .reg .b32 localVar; ... use N, dbl; other code; mov.b32 rval, result; ret; } ... call foo, (val0, val1); ...

.func (.param .u32 rval) bar(.param .u32 N, .param .align 4 .b8 numbers[]) { .reg .b32 input0, input1; ld.param.b32 input0, [numbers + 0]; ld.param.b32 input1, [numbers + 4]; ... other code; ret; } ...

.param .u32 N; .param .align 4 .b8 numbers[8]; st.param.u32 [N], 2; st.param.b32 [numbers + 0], 5; st.param.b32 [numbers + 4], 10; call (rval), bar, (N, numbers); ...

11.2.3. Kernel 与函数指示符：.alias

11.3. 控制流指示符

11.3.1. 控制流指示符：.branchtargets

.function bar() { .reg .u32 %r0; ... N0: ... N1: ... N2: ... N3: ... N4: ... ts: .branchtargets N<5>; @p brx.idx %r0, ts; ...

11.3.2. 控制流指示符：.calltargets

11.3.3. 控制流指示符：.callprototype

// example of array parameter Fproto5: .callprototype _ (.param .b8 _[12]);

Fproto6: .callprototype _ (.param .f32 _) .noreturn; ... @p call %r0, (%f1), Fproto6; ...

// example of .abi_preserve Fproto7: .callprototype _ (.param .b32 _) .abi_preserve 10; ... @p call %r0, (%r1), Fproto7; ...

11.4. 性能调优指示符

11.4.1. 性能调优指示符：.maxnreg

11.4.2. 性能调优指示符：.maxntid

11.4.3. 性能调优指示符：.reqntid

11.4.4. 性能调优指示符：.minnctapersm

11.4.5. 性能调优指示符：.maxnctapersm（已弃用）

11.4.6. 性能调优指示符：.noreturn

11.4.7. 性能调优指示符：.pragma

// disable unrolling for current kernel .entry foo .pragma "nounroll"; { ... }

11.4.8. 性能调优指示符：.abi_preserve

// Indirect call via call prototype .func (.param .b32 out[30]) foo (.param .b32 in[30]) .abi_preserve 10 { ... } ... mov.b64 lpfoo, foo; prot: .callprototype (.param .b32 out[30]) _ (.param .b32 in[30]) .abi_preserve 10; call (out), lpfoo, (in), prot;

11.4.9. 性能调优指示符：.abi_preserve_control

// Indirect call via call prototype .func (.param .b32 out[30]) bar (.param .b32 in[30]) .abi_preserve_control 10 { ... } ... mov.b64 lpbar, bar; prot: .callprototype (.param .b32 out[30]) _ (.param .b32 in[30]) .abi_preserve_control 10; call (out), lpbar, (in), prot;

11.4.10. 性能调优指示符：.minperctamemory

size = 32-bit unsigned integer (bytes)

11.5. 调试指示符

11.5.1. 调试指示符：@@dwarf

dwarf-string may have one of the .byte byte-list // comma-separated hexadecimal byte values .4byte int32-list // comma-separated hexadecimal integers in range [0..2^32-1] .quad int64-list // comma-separated hexadecimal integers in range [0..2^64-1] .4byte label .quad label

11.5.2. 调试指示符：.section

dwarf-lines have the following formats: .b8 byte-list // comma-separated list of integers // in range [-128..255] .b16 int16-list // comma-separated list of integers // in range [-2^15..2^16-1] .b32 int32-list // comma-separated list of integers // in range [-2^31..2^32-1] label: // Define label inside the debug section .b64 int64-list // comma-separated list of integers // in range [-2^63..2^64-1] .b32 label .b64 label .b32 label+imm // a sum of label address plus a constant integer byte // offset(signed, 32bit) .b64 label+imm // a sum of label address plus a constant integer byte // offset(signed, 64bit) .b32 label1-label2 // a difference in label addresses between labels in // the same dwarf section (32bit) .b64 label3-label4 // a difference in label addresses between labels in // the same dwarf section (64bit)

.section .debug_info { .b32 11430 .b8 2, 0 .b32 .debug_abbrev .b8 8, 1, 108, 103, 101, 110, 102, 101, 58, 32, 69, 68, 71, 32, 52, 46, 49 .b8 0 .b32 3, 37, 176, -99 .b32 info_label1 .b32 .debug_loc+0x4 .b8 -11, 11, 112, 97 .b32 info_label1+12 .b64 -1 .b16 -5, -65535 }

11.5.3. 调试指示符：.file

11.5.4. 调试指示符：.loc

.section .debug_str {
info_string0:
 .b8 95  // _
 .b8 90  // z
 .b8 51  // 3
 .b8 102 // f
 .b8 111 // o
 .b8 111 // o
 .b8 118 // v
 .b8 0

info_string1:
 .b8 95  // _
 .b8 90  // z
 .b8 51  // 3
 .b8 98  // b
 .b8 97  // a
 .b8 114 // r
 .b8 118 // v
 .b8 0
 .b8 95  // _
 .b8 90  // z
 .b8 51  // 3
 .b8 99  // c
 .b8 97  // a
 .b8 114 // r
 .b8 118 // v
 .b8 0
}

11.5.5. 调试指示符：.loc_intermediate

11.5.6. 调试指示符：.nv_intermediate_source_section

ir-name-string = quoted string identifier (e.g., "TileIR") file-index = unsigned integer matching a .file directive source-text = raw text of the intermediate IR source (heredoc)

11.6. 链接指示符

11.6.1. 链接指示符：.extern

11.6.2. 链接指示符：.visible

11.6.3. 链接指示符：.weak

11.6.4. 链接指示符：.common

11.7. Cluster 维度指示符

11.7.1. Cluster 维度指示符：.reqnctapercluster

11.7.2. Cluster 维度指示符：.explicitcluster

11.7.3. Cluster 维度指示符：.maxclusterrank

11.8. 杂项指示符

11.8.1. 杂项指示符：.blocksareclusters

11.8.2. 杂项指示符：.language

PTX ISA 9.4：12. Pragma 字符串

Mon, 28 Sep 2026 00:00:00 GMT

12.1. Pragma 字符串：“nounroll”

.func bar (...) { ... L1_head: .pragma "nounroll"; // do not unroll this loop ... @p bra L1_end; L1_body: ... L1_continue: bra L1_head; L1_end: ... }

12.2. Pragma 字符串：“used_bytes_mask”

// For 4 bytes load with only lower 3 bytes used .pragma "used_bytes_mask 0x7"; ld.global.u32 %r0, [gbl]; // Higher 1 byte from %r0 is unused

// For vector load of 16 bytes with lower 12 bytes used .pragma "used_bytes_mask 0xfff"; ld.global.v4.u32 {%r0, %r1, %r2, %r3}, [gbl]; // %r3 unused

12.3. Pragma 字符串：“enable_smem_spilling”

12.4. Pragma 字符串：“frequency”

12.5. Pragma 字符串：“mma_throughput”

PTX ISA 9.4：13. 发行说明

Mon, 28 Sep 2026 00:00:00 GMT

13.1. PTX ISA 9.4 版变更

13.2. PTX ISA 9.3 版变更

13.3. PTX ISA 9.2 版变更

13.4. PTX ISA 9.1 版变更

13.5. PTX ISA 9.0 版变更

13.6. PTX ISA 8.8 版变更

13.7. PTX ISA 8.7 版变更

13.8. PTX ISA 8.6 版变更

13.9. PTX ISA 8.5 版变更

13.10. PTX ISA 8.4 版变更

13.11. PTX ISA 8.3 版变更

13.12. PTX ISA 8.2 版变更

13.13. PTX ISA 8.1 版变更

13.14. PTX ISA 8.0 版变更

13.15. PTX ISA 7.8 版变更

13.16. PTX ISA 7.7 版变更

13.17. PTX ISA 7.6 版变更

13.18. PTX ISA 7.5 版变更

13.19. PTX ISA 7.4 版变更

13.20. PTX ISA 7.3 版变更

13.21. PTX ISA 7.2 版变更

13.22. PTX ISA 7.1 版变更

13.23. PTX ISA 7.0 版变更

13.24. PTX ISA 6.5 版变更

13.25. PTX ISA 6.4 版变更

13.26. PTX ISA 6.3 版变更

13.27. PTX ISA 6.2 版变更

13.28. PTX ISA 6.1 版变更

13.29. PTX ISA 6.0 版变更

13.30. PTX ISA 5.0 版变更

13.31. PTX ISA 4.3 版变更

13.32. PTX ISA 4.2 版变更

13.33. PTX ISA 4.1 版变更

13.34. PTX ISA 4.0 版变更

13.35. PTX ISA 3.2 版变更

13.36. PTX ISA 3.1 版变更

13.37. PTX ISA 3.0 版变更

13.38. PTX ISA 2.3 版变更

13.39. PTX ISA 2.2 版变更

13.40. PTX ISA 2.1 版变更

13.41. PTX ISA 2.0 版变更

PTX ISA 9.4：14. 声明

Mon, 28 Sep 2026 00:00:00 GMT

14.1. 版权声明

14.2. OpenCL

14.3. 商标

PTX ISA 9.4：2. 编程模型

Sat, 26 Sep 2026 00:00:00 GMT

2.1. 高度多线程的协处理器

GPU 是一种计算设备，能够并行执行大量线程。它作为主 CPU（即主机，host）的协处理器运行：也就是说，主机应用程序中数据并行且计算密集的部分会被卸载到设备上执行。

更具体地说，如果应用程序的一部分需要对不同数据彼此独立地重复执行多次，就可以将其抽取为一个 kernel 函数，再由 GPU 上的多个线程执行。为此，需要将该函数编译为 PTX 指令集，并在安装时将生成的 kernel 转换为目标 GPU 的指令集。

2.2. 线程层级

执行 kernel 的线程批次组织成一个 grid。grid 由协作线程数组（cooperative thread arrays，CTA）组成，也可以由 CTA 的集群组成；本节的说明与图 1和图 2相对应。CTA 对应 CUDA 线程块（thread block），集群对应 CUDA 线程块集群。

2.2.1. 协作线程数组

并行线程执行（Parallel Thread Execution，PTX）编程模型是显式并行的：一个 PTX 程序描述并行线程数组中单个线程的执行。协作线程数组（cooperative thread array，CTA）是并发或并行执行一个 kernel 的线程数组。

一个 CTA 内的线程可以相互通信。为了协调这些线程之间的通信，可以设置同步点，让线程在此等待，直到 CTA 中的所有线程都已到达。

一个 CTA 内的每个线程都有唯一的线程标识符。程序使用数据并行分解方法，将输入、工作和结果分配给 CTA 中的线程。每个 CTA 线程根据自身的线程标识符确定承担的任务、指定输入和输出的位置、计算地址，以及选择要执行的工作。线程标识符是一个三元素向量 tid（各元素为 tid.x、tid.y 和 tid.z），表示线程在一维、二维或三维 CTA 中的位置。在每个维度上，线程标识符分量从零开始，取值范围一直到该维度的线程数量。

每个 CTA 都有一维、二维或三维的形状，由三元素向量 ntid（各元素为 ntid.x、ntid.y 和 ntid.z）指定。向量 ntid 给出 CTA 在各个维度上的线程数量。

一个 CTA 内的线程以 SIMT（单指令多线程，single-instruction, multiple-thread）方式分组执行，这种分组称为 warp。一个 warp 是同一个 CTA 中能够同时执行相同指令的最大线程子集。warp 内的线程按顺序编号。warp 大小是依赖机器的常量，通常为 32 个线程。了解 warp 大小可能有助于某些应用最大化性能，因此 PTX 提供运行时立即数常量 WARP_SZ，可用于任何允许立即数操作数的指令。

2.2.2. 协作线程数组集群

集群是并发或并行运行的一组 CTA，它们可以通过共享内存相互同步和通信。执行中的 CTA 必须先确保对端 CTA 的共享内存已经存在，才能通过共享内存与其通信；在完成共享内存操作之前，还必须确保对端 CTA 尚未退出。

集群中不同 CTA 的线程可以通过共享内存相互同步和通信。可以使用集群范围的 barrier 来同步集群中的所有线程。集群中的每个 CTA 都有一个在该集群内唯一的 CTA 标识符（cluster_ctaid）。每个 CTA 集群由参数 cluster_nctaid 指定其一维、二维或三维形状。集群中的每个 CTA 还具有一个跨越所有维度的唯一 CTA 标识符（cluster_ctarank）；集群所有维度上的 CTA 总数由 cluster_nctarank 指定。线程可通过预定义的只读特殊寄存器 %cluster_ctaid、%cluster_nctaid、%cluster_ctarank 和 %cluster_nctarank 读取并使用这些值。

集群层级仅适用于目标架构 sm_90 或更高版本。启动 kernel 时可以选择是否指定集群层级。如果用户在启动时指定集群维度，这就是显式集群启动；否则就是维度默认为 1×1×1 的隐式集群启动。PTX 提供只读特殊寄存器 %is_explicit_cluster，用于区分显式和隐式集群启动。

2.2.3. 集群网格

一个 CTA 所能包含的线程数有上限，一个集群所能包含的 CTA 数量也有上限。不过，执行相同 kernel 的多个 CTA 集群可以合并成一个集群网格。这样，单次 kernel 调用就能启动非常多的线程，代价是线程间的通信和同步能力会降低，因为不同集群中的线程无法相互通信或同步。

每个集群在集群网格中都有唯一的集群标识符（clusterid）。每个集群网格的一维、二维或三维形状由参数 nclusterid 指定。每个网格还具有唯一的时间网格标识符（gridid）。线程可通过预定义的只读特殊寄存器 %tid、%ntid、%clusterid、%nclusterid 和 %gridid 读取并使用这些值。

每个 CTA 在网格中都有唯一标识符（ctaid）。每个 CTA 网格的一维、二维或三维形状由参数 nctaid 指定。线程可通过预定义的只读特殊寄存器 %ctaid 和 %nctaid 读取并使用这些值。

每个 kernel 都作为一批线程执行，这批线程组织成由 CTA 集群组成的网格；集群是可选层级，并且只适用于目标架构 sm_90 及更高版本。图 1展示由 CTA 组成的网格，图 2展示由集群组成的网格。

不同网格之间可以有启动依赖关系：一个网格可以是依赖网格，也可以是前置网格。有关如何定义网格依赖关系，请参阅《CUDA 编程指南》中的 CUDA Graphs 一节。

2.3. 内存层级

执行期间，PTX 线程可以访问多个状态空间中的数据，如图 3所示。目标架构从 sm_90 起引入了集群层级。每个线程都有私有的本地内存。每个线程块（CTA）都有共享内存；线程块中的所有线程，以及集群中所有活动线程块，都可以访问该共享内存。共享内存的生命周期与线程块相同。最后，所有线程都可以访问同一全局内存。

所有线程还可以访问其他状态空间：常量、参数（param）、纹理和表面状态空间。常量内存和纹理内存是只读的；表面内存则可读写。全局、常量、参数、纹理和表面状态空间针对不同的内存用途分别优化。例如，纹理内存提供不同的寻址模式，并能对特定数据格式进行过滤。

需要注意，纹理内存和表面内存都带有缓存。在同一次 kernel 调用期间，这些缓存与对全局内存或表面内存的写入并不保持一致。因此，如果某个地址在同一次 kernel 调用中被全局内存写入或表面内存写入，之后对该地址进行纹理读取或表面读取，结果是未定义的。换言之，只有在该纹理或表面内存位置已由先前的 kernel 调用或内存复制更新时，线程才能安全地读取它；如果该位置是在同一次 kernel 调用中由当前线程或其他线程更新的，则不能安全读取。

同一个应用程序的多次 kernel 启动之间，全局、常量和纹理状态空间会保持持久。

主机和设备各自都有本地内存，分别称为主机内存（host memory）和设备内存（device memory）。主机可以映射设备内存并对其读写。也可以通过优化的 API 调用，利用设备的高性能直接内存访问（Direct Memory Access，DMA）引擎，将数据从主机内存复制到设备内存，以实现更高效的传输。

PTX ISA 9.4：3. PTX 机器模型

Sat, 26 Sep 2026 00:00:00 GMT

3.1. 一组 SIMT 多处理器

NVIDIA GPU 架构以可扩展的多线程流式多处理器（Streaming Multiprocessors，SM）阵列为基础。主机程序启动一个 kernel grid 后，grid 中的线程块会被编号，并分配给有可用执行资源的多处理器。一个线程块中的线程会在同一个多处理器上并发执行。随着线程块执行完毕，新的线程块会被调度到腾出的多处理器上。

一个多处理器包含多个标量处理器（Scalar Processor，SP）核心、一个多线程指令单元和片上共享内存。多处理器在硬件中创建、管理和执行并发线程，无需调度开销。它支持单指令 barrier 同步。快速 barrier 同步、轻量级线程创建和零开销线程调度共同支持非常细粒度的并行；例如，可以用较小的粒度分解问题，为每个数据元素分配一个线程，例如图像中的像素、体数据中的体素，或基于网格的计算中的单元。

为了管理数百个同时运行的线程（这些线程可能执行多个不同的程序），多处理器采用了一种称为 **SIMT（单指令多线程，single-instruction, multiple-thread）**的架构。多处理器将每个线程映射到一个标量处理器核心，每个标量线程都能独立执行，并拥有各自的指令地址和寄存器状态。多处理器的 SIMT 单元按称为 warp 的并行线程组来创建、管理、调度和执行线程。（warp 一词源自织布，是早期并行线程技术中的术语。）组成一个 SIMT warp 的各个线程从同一程序地址同时开始执行，但除此之外，各自可以自由地分支和独立执行。

多处理器获得一个或多个线程块后，会将它们拆分为 warp，再交由 SIMT 单元调度。线程块拆分为 warp 的方式始终一致：每个 warp 包含线程标识符连续递增的线程，并且第一个 warp 从线程 0 开始。

在每次发射指令时，SIMT 单元都会选取一个已准备好执行的 warp，并向该 warp 中活动的线程发射下一条指令。一个 warp 在同一时刻执行一条共同指令；只有当 warp 内所有线程选择相同的执行路径时，执行效率才最高。如果 warp 内的线程由于依赖数据的条件分支而发生分歧（divergence），warp 会依次执行实际采用的各条分支路径，并暂时停用不在当前路径上的线程；所有路径执行完成后，线程会重新汇合到相同执行路径。分支分歧只会发生在单个 warp 内；不同 warp 相互独立执行，即使它们执行的是相同或完全不同的代码路径，也不会彼此影响。

SIMT 架构与 SIMD（单指令多数据，Single Instruction, Multiple Data）向量架构类似：一条指令控制多个处理单元。关键区别在于，SIMD 向量架构会把 SIMD 宽度暴露给软件，而 SIMT 指令描述的是单个线程的执行与分支行为。与 SIMD 向量机器不同，SIMT 让程序员可以针对相互独立的标量线程编写线程级并行代码，也可以针对彼此协作的线程编写数据并行代码。

为了保证正确性，程序员基本可以忽略 SIMT 的执行方式；不过，如果编写代码时尽量减少 warp 内线程的执行分歧，就可能获得显著的性能提升。这与传统代码中的缓存行类似：设计正确性时可以忽略缓存行大小，但要获得峰值性能，就需要在代码结构中考虑它。相比之下，向量架构要求软件显式地将加载操作合并成向量，并手动处理分歧。

一个多处理器能同时处理多少个线程块，取决于给定 kernel 所需的每线程寄存器数量和每块共享内存数量，因为多处理器的寄存器和共享内存要由批次中的所有线程块共同分配。如果多处理器可用的寄存器或共享内存不足以至少处理一个线程块，kernel 将无法启动。

一组带有片上共享内存的 SIMT 多处理器。

3.2. 独立线程调度

在 Volta 之前的架构上，一个 warp 的 32 个线程共用一个程序计数器，并使用活动掩码标记 warp 中当前活动的线程。因此，如果同一 warp 中的线程执行不同的分支路径或处于不同的执行状态，它们便不能相互发信号或交换数据。对于需要在锁或互斥量保护下细粒度共享数据的算法，竞争线程来自哪个 warp 可能导致死锁。

从 Volta 架构开始，独立线程调度（Independent Thread Scheduling）允许各线程充分并发，而不受 warp 边界限制。采用独立线程调度后，GPU 为每个线程维护执行状态，包括程序计数器和调用栈；GPU 还可以在线程粒度上暂停某个线程，以便更好地利用执行资源，或让某个线程等待另一个线程生成的数据。调度优化器会决定如何将同一 warp 中活动的线程分组到 SIMT 单元中。该机制保留了此前 NVIDIA GPU 上 SIMT 执行的高吞吐量，同时提供更大的灵活性：现在，线程可以在小于一个 warp 的粒度上发生分歧，并重新汇合。

如果开发者仍假设较早硬件架构的 warp 同步行为，独立线程调度可能使实际参与执行代码的线程集合与预期大不相同。尤其需要重新检查所有依赖 warp 同步的代码，例如不依赖同步操作的 warp 内归约，以确保它们与 Volta 及更新架构兼容。详情请参阅《CUDA 编程指南》中关于计算能力 7.x 的章节。

3.3. 片上共享内存

如图 4所示，每个多处理器都具有以下四类片上存储：

每个处理器都有一组本地 32 位寄存器。
共享内存是一种并行数据缓存，由所有标量处理器核心共享；共享内存空间位于此处。
常量缓存由所有标量处理器核心共享，只读，用于加速从常量内存空间读取数据。常量内存空间是设备内存中的一个只读区域。
纹理缓存由所有标量处理器核心共享，只读，用于加速从纹理内存空间读取数据。纹理内存空间是设备内存中的一个只读区域；每个多处理器都通过纹理单元访问纹理缓存，由纹理单元实现多种寻址模式和数据过滤。

本地内存空间和全局内存空间都是设备内存中可读写的区域。

PTX ISA 9.4：4. 语法

Sat, 26 Sep 2026 00:00:00 GMT

4.1. 源文件格式

4.2. 注释

4.3. 语句

start: mov.b32 r1, %tid.x; shl.b32 r1, r1, 2; // shift thread id by 2 bits ld.global.b32 r2, array[r1]; // thread[tid] gets array[tid] add.f32 r2, r2, 0.5; // add 1/2

4.3.1. 指示符语句

4.3.2. 指令语句

4.4. 标识符

4.5. 常量

4.5.1. 整数常量

4.5.2. 浮点常量

4.5.3. 谓词常量

4.5.4. 常量表达式

4.5.5. 整数常量表达式求值

4.5.6. 常量表达式求值规则汇总

PTX ISA 9.4：5. 状态空间、类型与变量

Sat, 26 Sep 2026 00:00:00 GMT

5.1. 状态空间

5.1.1. 寄存器状态空间

5.1.2. 特殊寄存器状态空间

5.1.3. 常量状态空间

5.1.3.1. 分 bank 常量状态空间（已弃用）

5.1.4. 全局状态空间

5.1.5. 局部状态空间

5.1.6. 参数状态空间

5.1.6.1. Kernel 函数参数

ld.param.u32 %n, [N];
ld.param.f64 %d, [buffer];
...

mov.u32      %ptr, len;
ld.param.u32 %n, [%ptr];
...

5.1.6.2. Kernel 函数参数属性

5.1.6.3. Kernel 参数属性：.ptr

.space = { .const, .global, .local, .shared };

5.1.6.4. 设备函数参数

ld.param.f64 %d, [buffer];
ld.param.s32 %y, [buffer+8];
...

}

// code snippet from the caller // struct { double d; int y; } mystruct; is flattened, passed to foo ... .reg .f64 dbl; .reg .s32 x; .param .align 8 .b8 mystruct; ... st.param.f64 [mystruct+0], dbl; st.param.s32 [mystruct+8], x; call foo, (4, mystruct); ...

ld.param.u32 %n, [N];
mov.u32      %r, buffer;  // forces buffer to .local state space

Loop: setp.eq.u32 %p, %n, 0; @%p bra Done; ld.local.f32 %f, [%r]; ... add.u32 %r, %r, 4; sub.u32 %n, %n, 1; bra Loop; Done: ... }

5.1.7. 共享状态空间

5.1.8. 纹理状态空间（已弃用）

5.2. 类型

5.2.1. 基本类型

5.2.2. 子字宽的受限使用

5.2.3. 其他浮点数据格式

5.2.4. 定点数据格式

5.2.5. 打包数据类型

5.2.5.1. 打包浮点数据类型

5.2.5.2. 打包整数数据类型

5.2.5.3. 打包定点数据类型

5.3. 纹理、采样器与表面类型

5.3.1. 纹理与表面属性

5.3.2. 采样器属性

5.3.3. 通道数据类型与通道顺序字段

5.4. 变量

5.4.1. 变量声明

5.4.2. 向量

5.4.3. 数组声明

5.4.4. 初始化器

// array of generic-address pointers to elements of bar .global .u32 parr[] = { generic(bar), generic(bar)+4, generic(bar)+8 };

// examples using mask() operator are pruned for brevity .global .u8 addr[] = {0xff(foo), 0xff00(foo), 0xff0000(foo), ...};

.global .u8 addr2[] = {0xff(foo+4), 0xff00(foo+4), 0xff0000(foo+4),...}

.global .u8 addr3[] = {0xff(generic(foo)), 0xff00(generic(foo)),...}

.global .u8 addr4[] = {0xff(generic(foo)+4), 0xff00(generic(foo)+4),...}

// mask() operator with integer const expression .global .u8 addr5[] = { 0xFF(1000 + 546), 0xFF00(131187), ...};

.global .u32 foo[] = { 2, 3, 5, 7, 9, 11 }; .global .u64 ptr = generic(foo); // generic address of foo[0] .global .u64 ptr = generic(foo)+8; // generic address of foo[2]

5.4.5. 对齐

5.4.6. 参数化变量名

5.4.7. 变量属性

5.4.8. 变量和函数属性指示符：.attribute

.global .attribute(.unified(19,95)) .f32 f;

.func .attribute(.unified(0xAB, 0xCD)) bar() { ... }

5.5. 张量

5.5.1. 张量维度、大小与格式

5.5.1.1. 子字节类型

5.5.1.1.1. 子字节类型的填充与对齐

5.5.2. 张量访问模式

5.5.3. Tiled 模式

5.5.3.1. 边界框

5.5.3.2. 遍历步长

5.5.3.3. 越界访问

5.5.3.4. .tile::scatter4 与 .tile::gather4 模式

5.5.3.4.1. 边界框

5.5.4. im2col 模式

5.5.4.1. 边界框

tensor coordinates = (7, 7, 4, 0) im2col offsets : (0, 0)

tensor coordinates = (7, 7, 4, 0) im2col offsets: (2, 2)

5.5.4.2. 遍历步长

5.5.4.3. 越界访问

5.5.5. im2col::w、im2col_no_offs::w 与 im2col::w::128 模式

5.5.5.1. 边界框

5.5.5.2. 遍历步长

5.5.5.3. wHalo

Tensor Coordinates in the instruction = (7, 2, 3, 0) wHalo in the instruction = 2 (as 3x3 convolution filter is used)

5.5.5.4. wOffset

Tensor Coordinates in the instruction = (7, 2, -1, 0)

Shared memory buffer 1: wHalo = 1 wOffset = 0

Shared memory buffer 2: wHalo = 0 wOffset = 1

Tensor Coordinates in the instruction = (7, 2, -1, 0)

Shared memory buffer 1: wHalo = 0 wOffset = 0

Shared memory buffer 2: wHalo = 0 wOffset = 1

Shared memory buffer 3: wHalo = 0 wOffset = 2

5.5.6. 交错布局

5.5.7. 重排模式

5.5.8. Tensor-map

PTX ISA 9.4：6. 指令操作数

Sat, 26 Sep 2026 00:00:00 GMT

6.1. 操作数类型信息

6.2. 源操作数

6.3. 目标操作数

6.4. 使用地址、数组与向量

6.4.1. 作为操作数的地址

ld.shared.u16 r0,[x]; ld.global.v4.f32 W, [V]; ld.const.s32 q, [tbl+12]; mov.u32 p, tbl;

6.4.1.1. 通用寻址

6.4.2. 作为操作数的数组

6.4.3. 作为操作数的向量

mov.v4.f32 {a,b,c,d}, V;

6.4.4. 作为操作数的标号与函数名

6.5. 类型转换

6.5.1. 标量转换

6.5.2. 舍入修饰符

6.6. 操作数开销

PTX ISA 9.4：7. ABI 抽象

Sat, 26 Sep 2026 00:00:00 GMT

7. ABI 抽象

7.1. 函数声明和定义

...
call foo;
...

...
call (%r1), inc_ptr, (%r1,4);
...

{ .param .b8 .align 8 py[12]; ... st.param.b64 [py+ 0], %rd; st.param.b8 [py+ 8], %rc1; st.param.b8 [py+ 9], %rc2; st.param.b8 [py+10], %rc1; st.param.b8 [py+11], %rc2; // scalar args in .reg space, byte array in .param space call (%out), bar, (%x, py); ...

7.1.1. 与 PTX ISA 1.x 相比的变化

7.2. 可变参数函数

7.3. Alloca

PTX ISA 9.4：8. 内存一致性模型

Sat, 26 Sep 2026 00:00:00 GMT

8.1. 模型的范围与适用性

8.1.1. 系统作用域下原子性的限制

8.2. 内存操作

8.2.1. 重叠

8.2.2. 别名

8.2.3. Multimem 地址

8.2.4. 向量数据类型的内存操作

8.2.5. 打包数据类型的内存操作

8.2.6. 初始化

8.3. 状态空间

8.4. 操作类型

8.4.1. mmio 操作

8.4.2. volatile 操作

8.5. 作用域

8.6. 代理

8.6.1. 强代理访问

8.7. 道德强操作

8.7.1. 冲突与数据竞争

8.7.2. 混合大小数据竞争的限制

8.8. 释放与获取模式

8.9. 内存操作的顺序

8.9.1. 程序顺序

8.9.1.1. 异步操作

8.9.2. 观察序

8.9.3. fence.sc 序

8.9.4. 内存同步

8.9.5. 因果序

8.9.6. 一致性序

8.9.7. 通信序

8.10. 公理

8.10.1. 一致性

8.10.2. Fence-SC

8.10.3. 原子性

8.10.4. 无薄空气

8.10.5. 每个位置的顺序一致性

8.10.6. 因果性

8.11. 特殊情况

8.11.1. 归约不构成获取模式

PTX ISA 9.4：9. 指令集

Sat, 26 Sep 2026 00:00:00 GMT

9.1. 指令描述的格式和语义

9.2. PTX 指令

9.3. 谓词执行

9.3.1. 比较

9.3.1.1. 整数和位宽类型比较

9.3.1.2. 浮点比较

9.3.2. 谓词操作

9.4. 指令和操作数的类型信息

add.u16 d, a, b; // perform a 16-bit unsigned add

cvt.f32.u16 d, a; // convert 16-bit unsigned to 32-bit float

9.4.1. 操作数宽度超过指令类型宽度

9.5. 控制结构中的线程分歧

9.6. 语义

9.6.1. 16 位代码的机器相关语义

9.7. 指令

9.7.1. 整数算术指令

9.7.1.1. 整数算术指令：add

.type1 = { .u16, .u64, .s16, .s64 };

.type2 = { .u32, .u16x2, .u8x4, .s32, .s16x2, .s8x4 };

9.7.1.2. 整数算术指令：sub

.type1 = { .u16, .u32, .u64, .s16, .s64 };

.type2 = { .s32, .u8x4, .s8x4 };

9.7.1.3. 整数算术指令：mul

.mode = { .hi, .lo, .wide }; .type = { .u16, .u32, .u64, .s16, .s32, .s64 };

9.7.1.4. 整数算术指令：mad

.mode = { .hi, .lo, .wide }; .type = { .u16, .u32, .u64, .s16, .s32, .s64 };

9.7.1.5. 整数算术指令：clmad

.mode = { .hi, .lo };

for (i = 0; i < 64; i++) { if ((a & (1 << i)) != 0) { tmp ^= b << i; } }

// Select upper or lower 64 bits depending on the value of .mode. if (.mode == .lo) { d = tmp[63..0]; } else { d = tmp[127..64]; }

d ^= c; // carryless accumulation.

// Carryless multiply-add producing lower 64 bits of result. clmad.lo.u64 Rd, Ra, Rb, Rc;

// Carryless multiply-add producing higher 64 bits of result. clmad.hi.u64 Rd, Ra, Rb, Rc;

9.7.1.6. 整数算术指令：mul24

.mode = { .hi, .lo }; .type = { .u32, .s32 };

9.7.1.7. 整数算术指令：mad24

.mode = { .hi, .lo }; .type = { .u32, .s32 };

9.7.1.8. 整数算术指令：sad

.type = { .u16, .u32, .u64, .s16, .s32, .s64 };

9.7.1.9. 整数算术指令：div

.type = { .u16, .u32, .u64, .s16, .s32, .s64 };

9.7.1.10. 整数算术指令：rem

.type = { .u16, .u32, .u64, .s16, .s32, .s64 };

9.7.1.11. 整数算术指令：abs

.type = { .s16, .s32, .s64 };

9.7.1.12. 整数算术指令：neg

.type = { .s8x4, .s16, .s32, .s64 };

9.7.1.13. 整数算术指令：min

.type1 = { .u16, .u32, .u64, .u16x2, .u8x4, .s16, .s64 }; .type2 = { .s16x2, .s32, .s8x4 };

9.7.1.14. 整数算术指令：max

.type1 = { .u16, .u32, .u64, .u16x2, .u8x4, .s16, .s64 }; .type2 = { .s16x2, .s32, .s8x4 };

9.7.1.15. 整数算术指令：popc

.type = { .b32, .b64 };

9.7.1.16. 整数算术指令：clz

.type = { .b32, .b64 };

while (d < max && (a&mask == 0) ) { d++; a = a << 1; }

9.7.1.17. 整数算术指令：bfind

.type = { .u32, .u64, .s32, .s64 };

9.7.1.18. 整数算术指令：fns

while ((pos &gt;= 0) &amp;&amp; (pos &lt; 32)) {
    if (mask[pos] == 1) {
        if (count == 0) {
          d = pos;
          break;
       } else {
           count = count - 1;
       }
    }
    pos = pos + inc;
}

}

9.7.1.19. 整数算术指令：brev

.type = { .b32, .b64 };

for (i=0; i<=msb; i++) { d[i] = a[msb-i]; }

9.7.1.20. 整数算术指令：bfe

.type = { .u32, .u64, .s32, .s64 };

if (.type==.u32 || .type==.u64 || len==0) sbit = 0; else sbit = a[min(pos+len-1,msb)];

d = 0; for (i=0; i<=msb; i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit; }

9.7.1.21. 整数算术指令：bfi

.type = { .b32, .b64 };

f = b; for (i=0; i<len && pos+i<=msb; i++) { f[pos+i] = a[i]; }

9.7.1.22. 整数算术指令：szext

.mode = { .clamp, .wrap }; .type = { .u32, .s32 };

if (b1 == 0 || too_large || .type != .s32) { sign_bit = false; } else { sign_bit = (a >> sign_pos) & 1; } d = (a & ~mask) | (sign_bit ? mask | 0);

9.7.1.23. 整数算术指令：bmsk

.mode = { .clamp, .wrap };

sum-overflow = sum >= 32 ? true : false; bit-position-overflow = false; bit-width-overflow = false;

if (.mode == .clamp) { if (a >= 32) { bit-position-overflow = true; mask0 = 0; } if (b >= 32) { bit-width-overflow = true; } }

if (sum-overflow || bit-position-overflow || bit-width-overflow) { mask1 = 0; } else if (b1 == 0) { mask1 = ~0; } d = mask0 & ~mask1;

9.7.1.24. 整数算术指令：dp4a

.atype = .btype = { .u32, .s32 };

// Extract 4 bytes from a 32bit input and sign or zero extend // based on input type. Va = extractAndSignOrZeroExt_4(a, .atype); Vb = extractAndSignOrZeroExt_4(b, .btype);

for (i = 0; i < 4; ++i) { d += Va[i] * Vb[i]; }

9.7.1.25. 整数算术指令：dp2a

.atype = .btype = { .u32, .s32 }; .mode = { .lo, .hi };

// Extract four 8-bit values from a 32-bit input and sign or zer extend // based on input type. Vb = extractAndSignOrZeroExt_4(b, .btype);

b_select = (.mode == .lo) ? 0 : 2;

for (i = 0; i < 2; ++i) { d += Va[i] * Vb[b_select + i]; }

9.7.2. 扩展精度整数算术指令

9.7.2.1. 扩展精度算术指令：add.cc

.type = { .u32, .s32, .u64, .s64 };

9.7.2.2. 扩展精度算术指令：addc

.type = { .u32, .s32, .u64, .s64 };

9.7.2.3. 扩展精度算术指令：sub.cc

.type = { .u32, .s32, .u64, .s64 };

9.7.2.4. 扩展精度算术指令：subc

.type = { .u32, .s32, .u64, .s64 };

9.7.2.5. 扩展精度算术指令：mad.cc

.type = { .u32, .s32, .u64, .s64 };

9.7.2.6. 扩展精度算术指令：madc

.type = { .u32, .s32, .u64, .s64 };

9.7.3. 浮点指令

9.7.3.1. 浮点指令：testp

.op = { .finite, .infinite, .number, .notanumber, .normal, .subnormal }; .type = { .f32, .f64 };

9.7.3.2. 浮点指令：copysign

.type = { .f32, .f64 };

9.7.3.3. 浮点指令：add

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.4. 浮点指令：sub

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.5. 浮点指令：mul

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.6. 浮点指令：fma

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.7. 浮点指令：mad

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.8. 浮点指令：div

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.9. 浮点指令：abs

9.7.3.10. 浮点指令：neg

9.7.3.11. 浮点指令：min

def min_nan (z, x, y) { if (isNaN(x) || isNaN(y)) z = NaN; else // note: -0.0 < +0.0 here z = (x < y) ? x : y; return z; }

def two_inputs_min (z, x, y) { if (.NaN) z = min_nan(z, x, y); else z = min_num(z, x, y); return z; }

if (.xorsign && !isPresent(c)) { xorsign = getSignBit(a) ^ getSignBit(b); } if (.abs) { a = |a|; b = |b|; if (isPresent(c)) { c = |c|; } }

d = two_inputs_min(d, a, b) if (isPresent(c)) { d = two_inputs_min(d, d, c) } if (.xorsign && !isPresent(c) && !isNaN(d)) { setSignBit(d, xorsign); }

9.7.3.12. 浮点指令：max

def max_nan (z, x, y) { if (isNaN(x) || isNaN(y)) z = NaN; else // note: +0.0 > -0.0 here z = (x > y) ? x : y; return z; }

def two_inputs_max (z, x, y) { if (.NaN) z = max_nan(z, x, y); else z = max_num(z, x, y); return z; }

if (.xorsign && !isPresent(c)) { xorsign = getSignBit(a) ^ getSignBit(b); } if (.abs) { a = |a|; b = |b|; if (isPresent(c)) { c = |c|; } }

d = two_inputs_max (d, a, b) if (isPresent(c)) { d = two_inputs_max (d, d, c) }

if (.xorsign && !isPresent(c) !isNaN(d)) { setSignBit(d, xorsign); }

9.7.3.13. 浮点指令：rcp

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.14. 浮点指令：rcp.approx.ftz.f64

9.7.3.15. 浮点指令：sqrt

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.16. 浮点指令：rsqrt

9.7.3.17. 浮点指令：rsqrt.approx.ftz.f64

9.7.3.18. 浮点指令：sin

9.7.3.19. 浮点指令：cos

9.7.3.20. 浮点指令：lg2

9.7.3.21. 浮点指令：ex2

9.7.3.22. 浮点指令：tanh

9.7.4. 半精度浮点指令

9.7.4.1. 半精度浮点指令：add

add{.rnd}.bf16 d, a, b; add{.rnd}.bf16x2 d, a, b;

.rnd = { .rn };

// SIMD f16 addition cvt.rn.f16.f32 h0, f0; cvt.rn.f16.f32 h1, f1; cvt.rn.f16.f32 h2, f2; cvt.rn.f16.f32 h3, f3; mov.b32 p1, {h0, h1}; // pack two f16 to 32bit f16x2 mov.b32 p2, {h2, h3}; // pack two f16 to 32bit f16x2 add.f16x2 p3, p1, p2; // SIMD f16x2 addition

// SIMD bf16 addition cvt.rn.bf16x2.f32 p4, f4, f5; // Convert two f32 into packed bf16x2 cvt.rn.bf16x2.f32 p5, f6, f7; // Convert two f32 into packed bf16x2 add.bf16x2 p6, p4, p5; // SIMD bf16x2 addition

// SIMD fp16 addition ld.global.b32 f0, [addr]; // load 32 bit which hold packed f16x2 ld.global.b32 f1, [addr + 4]; // load 32 bit which hold packed f16x2 add.f16x2 f2, f0, f1; // SIMD f16x2 addition

ld.global.b32 f3, [addr + 8]; // load 32 bit which hold packed bf16x2 ld.global.b32 f4, [addr + 12]; // load 32 bit which hold packed bf16x2 add.bf16x2 f5, f3, f4; // SIMD bf16x2 addition

9.7.4.2. 半精度浮点指令：sub

sub{.rnd}.bf16 d, a, b; sub{.rnd}.bf16x2 d, a, b;

.rnd = { .rn };

// SIMD f16 subtraction cvt.rn.f16.f32 h0, f0; cvt.rn.f16.f32 h1, f1; cvt.rn.f16.f32 h2, f2; cvt.rn.f16.f32 h3, f3; mov.b32 p1, {h0, h1}; // pack two f16 to 32bit f16x2 mov.b32 p2, {h2, h3}; // pack two f16 to 32bit f16x2 sub.f16x2 p3, p1, p2; // SIMD f16x2 subtraction

// SIMD bf16 subtraction cvt.rn.bf16x2.f32 p4, f4, f5; // Convert two f32 into packed bf16x2 cvt.rn.bf16x2.f32 p5, f6, f7; // Convert two f32 into packed bf16x2 sub.bf16x2 p6, p4, p5; // SIMD bf16x2 subtraction

// SIMD fp16 subtraction ld.global.b32 f0, [addr]; // load 32 bit which hold packed f16x2 ld.global.b32 f1, [addr + 4]; // load 32 bit which hold packed f16x2 sub.f16x2 f2, f0, f1; // SIMD f16x2 subtraction

// SIMD bf16 subtraction ld.global.b32 f3, [addr + 8]; // load 32 bit which hold packed bf16x2 ld.global.b32 f4, [addr + 12]; // load 32 bit which hold packed bf16x2 sub.bf16x2 f5, f3, f4; // SIMD bf16x2 subtraction

9.7.4.3. 半精度浮点指令：mul

mul{.rnd}.bf16 d, a, b; mul{.rnd}.bf16x2 d, a, b;

.rnd = { .rn };

// SIMD f16 multiplication cvt.rn.f16.f32 h0, f0; cvt.rn.f16.f32 h1, f1; cvt.rn.f16.f32 h2, f2; cvt.rn.f16.f32 h3, f3; mov.b32 p1, {h0, h1}; // pack two f16 to 32bit f16x2 mov.b32 p2, {h2, h3}; // pack two f16 to 32bit f16x2 mul.f16x2 p3, p1, p2; // SIMD f16x2 multiplication

// SIMD bf16 multiplication cvt.rn.bf16x2.f32 p4, f4, f5; // Convert two f32 into packed bf16x2 cvt.rn.bf16x2.f32 p5, f6, f7; // Convert two f32 into packed bf16x2 mul.bf16x2 p6, p4, p5; // SIMD bf16x2 multiplication

// SIMD fp16 multiplication ld.global.b32 f0, [addr]; // load 32 bit which hold packed f16x2 ld.global.b32 f1, [addr + 4]; // load 32 bit which hold packed f16x2 mul.f16x2 f2, f0, f1; // SIMD f16x2 multiplication

// SIMD bf16 multiplication ld.global.b32 f3, [addr + 8]; // load 32 bit which hold packed bf16x2 ld.global.b32 f4, [addr + 12]; // load 32 bit which hold packed bf16x2 mul.bf16x2 f5, f3, f4; // SIMD bf16x2 multiplication

9.7.4.4. 半精度浮点指令：fma

.rnd = { .rn };

// scalar bf16 fused multiply-add fma.rn.bf16 d1, a1, b1, c1; fma.rn.relu.bf16 d1, a1, b1, c1; fma.rn.oob.bf16 d1, a1, b1, c1; fma.rn.oob.relu.bf16 d1, a1, b1, c1;

// SIMD f16 fused multiply-add cvt.rn.f16.f32 h0, f0; cvt.rn.f16.f32 h1, f1; cvt.rn.f16.f32 h2, f2; cvt.rn.f16.f32 h3, f3; mov.b32 p1, {h0, h1}; // pack two f16 to 32bit f16x2 mov.b32 p2, {h2, h3}; // pack two f16 to 32bit f16x2 fma.rn.f16x2 p3, p1, p2, p2; // SIMD f16x2 fused multiply-add fma.rn.relu.f16x2 p3, p1, p2, p2; // SIMD f16x2 fused multiply-add with relu saturation mode fma.rn.oob.f16x2 p3, p1, p2, p2; // SIMD f16x2 fused multiply-add with oob modifier fma.rn.oob.relu.f16x2 p3, p1, p2, p2; // SIMD f16x2 fused multiply-add with oob modifier and relu saturation mode

// SIMD fp16 fused multiply-add ld.global.b32 f0, [addr]; // load 32 bit which hold packed f16x2 ld.global.b32 f1, [addr + 4]; // load 32 bit which hold packed f16x2 fma.rn.f16x2 f2, f0, f1, f1; // SIMD f16x2 fused multiply-add

// SIMD bf16 fused multiply-add fma.rn.bf16x2 f2, f0, f1, f1; // SIMD bf16x2 fused multiply-add fma.rn.relu.bf16x2 f2, f0, f1, f1; // SIMD bf16x2 fused multiply-add with relu saturation mode fma.rn.oob.bf16x2 f2, f0, f1, f1; // SIMD bf16x2 fused multiply-add with oob modifier fma.rn.oob.relu.bf16x2 f2, f0, f1, f1; // SIMD bf16x2 fused multiply-add with oob modifier and relu saturation mode

9.7.4.5. 半精度浮点指令：neg

9.7.4.6. 半精度浮点指令：abs

9.7.4.7. 半精度浮点指令：min

9.7.4.8. 半精度浮点指令：max

9.7.4.9. 半精度浮点指令：tanh

.type = {.f16, .f16x2, .bf16, .bf16x2}

9.7.4.10. 半精度浮点指令：ex2

.atype = { .f16, .f16x2} .btype = { .bf16, .bf16x2}

9.7.5. 混合精度浮点指令

9.7.5.1. 混合精度浮点指令：add

add{.rnd}.dtype2.atype2.ctype2 d, a, c; add.rz.ftz.dtype3.atype3.ctype2 d, a, c; add.rz.dtype4.atype3.ctype2 d, a, c;

.atype = { .f16, .bf16 }; .cdtype = { .f32 }; .atype2 = { .f16x2, .bf16x2 }; .dtype2 = .ctype2 = .atype3 = { .f32x2 }; .dtype3 = { .f16x2 }; .dtype4 = { .bf16x2 }; .rnd = { .rn, .rz, .rm, .rp };

9.7.5.2. 混合精度浮点指令：sub

.atype = { .f16, .bf16 }; .rnd = { .rn, .rz, .rm, .rp }; .cdtype = { .f32 }; .atype2 = { .f16x2, .bf16x2 }; .dtype2 = .ctype2 = .atype3 = { .f32x2 }; .dtype3 = { .f16x2 }; .dtype4 = { .bf16x2 };

9.7.5.3. 混合精度浮点指令：fma

.abtype = { .f16, .bf16 }; .cdtype = { .f32 }; .atype = { .f16x2, .bf16x2 }; .btype = .ctype = .dtype = { .f32x2 }; .rnd = { .rn, .rz, .rm, .rp };

9.7.5.4. 混合精度浮点指令：mul

.dtype1 = { .f16x2 } .dtype2 = { .bf16x2 } .atype1 = .ctype1 = { .f32x2 } .dtype3 = .atype2 = { .bf16x2 } .ctype2 = { .f16x2 } .dtype4 = .atype3 = { .f16x2 } .ctype3 = { .bf16x2 }

9.7.6. 其他浮点指令

9.7.6.1. 其他浮点指令：add

.cdtype = { .e5m2x4, .e4m3x4 }; .atype = { .e5m2x4, .e4m3x4, .e3m2x4, .e2m3x4, .e2m1x4, .e2m1p4x4, .ue8m0x4 }; .rnd = { .rn };

iC[0] = c[0:7]; iC[1] = c[8:15]; iC[2] = c[16:23]; iC[3] = c[24:31];

for (i = 0; i < 4; i++) { d[i] = iA[i] + iC[i]; }

// f8x4 addition mov.b32 ra, {ba0, ba1, ba2, ba3}; // pack four f8 as f8x4 mov.b32 rc, {bc0, bc1, bc2, bc3}; // pack four f8 as f8x4 add.rn.e5m2x4.e4m3x4.satfinite rd, ra, rc; // SIMD addition

// f4x4 and f8x4 addition .reg .b16 ra16; mov.b16 ra16, {ba0, ba1}; // pack four f4 as f4x4 in b16 operand mov.b32 rc, {bc0, bc1, bc2, bc3}; // pack four f8 as f8x4 add.rn.e4m3x4.e2m1x4 rd, ra16, rc; // SIMD addition

// f4x4 (padded) and f8x4 addition mov.b32 ra, {ba0, ba1, ba2, ba3}; // pack four f4 as f4x4 in b32. Each f4 resides within lower half of a byte mov.b32 rc, {bc0, bc1, bc2, bc3}; // pack four f8 as f8x4 add.rn.e4m3x4.e2m1p4x4 rd, ra, rc;

9.7.6.2. 其他浮点指令：sub

.cdtype = { .e5m2x4, .e4m3x4 }; .atype = { .e5m2x4, .e4m3x4, .e3m2x4, .e2m3x4, .e2m1x4, .e2m1p4x4, .ue8m0x4 }; .rnd = { .rn };

iC[0] = c[0:7]; iC[1] = c[8:15]; iC[2] = c[16:23]; iC[3] = c[24:31];

for (i = 0; i < 4; i++) { d[i] = iA[i] - iC[i]; }

// subtraction of f8x4 from ue8m0x4 mov.b32 ra, {ba0, ba1, ba2, ba3}; // pack four ue8m0 values mov.b32 rc, {bc0, bc1, bc2, bc3}; // pack four f8 as f8x4 sub.rn.e5m2x4.ue8m0x4.satfinite rd, ra, rc;

// subtraction of f6x4 from f8x4 mov.b32 ra, {ba0, ba1, ba2, ba3}; // pack four f6 as f6x4 mov.b32 rc, {bc0, bc1, bc2, bc3}; // pack four f8 as f8x4 sub.rn.e5m2x4.e2m3x4.satfinite rd, ra, rc; // SIMD subtraction

// subtraction of f8x4 from f4x4 .reg .b16 ra16; mov.b16 ra16, {ba0, ba1}; // pack four f4 as f4x4 in b16 operand mov.b32 rc, {bc0, bc1, bc2, bc3}; // pack four f8 as f8x4 sub.rn.e4m3x4.e2m1x4 rd, ra16, rc; // SIMD subtraction

9.7.6.3. 其他浮点指令：mul

.dtype = { .e5m2x4, .e4m3x4 }; .atype = .ctype = { .e5m2x4, .e4m3x4, .e3m2x4, .e2m3x4, .e2m1x4, .e2m1p4x4, .ue8m0x4 }; .rnd = { .rn };

if (isF8x4(ctype) || isUE8M0x4(ctype)) { iC[0] = c[0:7]; iC[1] = c[8:15]; iC[2] = c[16:23]; iC[3] = c[24:31]; } else if (isF6x4(ctype)) { iC[0] = c[0:5]; iC[1] = c[8:13]; iC[2] = c[16:21]; iC[3] = c[24:29]; } else if (isE2M1P4x4(ctype)) { iC[0] = c[0:3]; iC[1] = c[8:11]; iC[2] = c[16:19]; iC[3] = c[24:27]; } else if (isE2M1x4(ctype)) { iC[0] = c[0:3]; iC[1] = c[4:7]; iC[2] = c[8:11]; iC[3] = c[12:15]; }

for (i = 0; i < 4; i++) { d[i] = iA[i] * iC[i]; }

// multiplication of f6x4 with f4x4 to obtain f8x4 mov.b32 ra, {ba0, ba1, ba2, ba3}; // pack four f6 as f6x4 .reg .b16 rc16; mov.b16 rc16, {bc0, bc1}; // pack four f4 as f4x4 in .b16 operand mul.rn.e5m2x4.e3m2x4.e2m1x4.satfinite rd, ra, rc16; // SIMD multiplication

// multiplication of ue8m0x4 with f8x4 to obtain f8x4 mov.b32 ra, {ba0, ba1, ba2, ba3}; // pack four ue8m0 values mov.b32 rc, {bc0, bc1, bc2, bc3}; // pack four f8 as f8x4 mul.rn.e4m3x4.ue8m0x4.e5m2x4 rd, ra, rc; // SIMD multiplication

// multiplication of f6x4 with f6x4 to obtain f8x4 mov.b32 ra, {ba0, ba1, ba2, ba3}; // pack four f6 as f6x4 mov.b32 rc, {bc0, bc1, bc2, bc3}; // pack four f6 as f6x4 mul.rn.e5m2x4.e3m2x4.e2m3x4.satfinite rd, ra, rc; // SIMD multiplication

9.7.6.4. 其他浮点指令：fma

.cdtype = { .e5m2x4, .e4m3x4 }; .atype = .btype = { .e5m2x4, .e4m3x4, .e3m2x4, .e2m3x4, .e2m1x4, .e2m1p4x4, .ue8m0x4 }; .rnd = { .rn };

if (isF8x4(btype) || isUE8M0x4(btype)) { iB[0] = b[0:7]; iB[1] = b[8:15]; iB[2] = b[16:23]; iB[3] = b[24:31]; } else if (isF6x4(btype)) { iB[0] = b[0:5]; iB[1] = b[8:13]; iB[2] = b[16:21]; iB[3] = b[24:29]; } else if (isE2M1P4x4(btype)) { iB[0] = b[0:3]; iB[1] = b[8:11]; iB[2] = b[16:19]; iB[3] = b[24:27]; } else if (isE2M1x4(btype)) { iB[0] = b[0:3]; iB[1] = b[4:7]; iB[2] = b[8:11]; iB[3] = b[12:15]; }

iC[0] = c[0:7]; iC[1] = c[8:15]; iC[2] = c[16:23]; iC[3] = c[24:31];

for (i = 0; i < 4; i++) { d[i] = iA[i] * iB[i] + iC[i]; }

// multiply ue8m0x4 with f4x4 and add f8x4 mov.b32 ra, {ba0, ba1, ba2, ba3}; // pack four ue8m0 mov.b32 rb, {bb0, bb1, ba2, ba3}; // pack four f4 as f4x4 in b32 operand. Each f4 resides within lower half of a byte. mov.b32 rc, {ba0, ba1, ba2, ba3}; // pack four f8 as f8x4 fma.rn.e5m2x4.ue8m0x4.e2m1p4x4.satfinite rd, ra, rb, rc;

// multiply f6x4 with f4x4 and add f8x4 mov.b32 ra, {ba0, ba1, ba2, ba3}; // pack four f6 as f6x4 .reg .b16 rb16; mov.b16 rb16, {bb0, bb1}; // pack four f4 as f4x4 in .b16 operand mov.b32 rc, {ba0, ba1, ba2, ba3}; // pack four f8 as f8x4 fma.rn.e4m3x4.e3m2x4.e2m1x4.satfinite rd, ra, rb16, rc; // SIMD fused-multiply-add

// multiply ue8m0x4 with f8x4 and add f8x4 mov.b32 ra, {ba0, ba1, ba2, ba3}; // pack four ue8m0 values mov.b32 rb, {bb0, bb1, bb2, bb3}; // pack four f8 as f8x4 mov.b32 rc, {ba0, ba1, ba2, ba3}; // pack four f8 as f8x4 fma.rn.e4m3x4.ue8m0x4.e5m2x4 rd, ra, rb, rc; // SIMD fused-multiply-add

9.7.7. 比较和选择指令

9.7.7.1. 比较和选择指令：set

.CmpOp = { eq, ne, lt, le, gt, ge, lo, ls, hi, hs, equ, neu, ltu, leu, gtu, geu, num, nan }; .BoolOp = { and, or, xor }; .dtype = { .u32, .s32, .f32 }; .stype = { .b16, .b32, .b64, .u16, .u32, .u64, .s16, .s32, .s64, .f32, .f64 };

set.CmpOp.type d, a, b;

.CmpOp = { eq, ne, lt, le, gt, ge, lo, ls, hi, hs}; .type = { .u8x4, .s8x4, .u16x2, .s16x2 };

9.7.7.2. 比较和选择指令：setp

.CmpOp = { eq, ne, lt, le, gt, ge, lo, ls, hi, hs, equ, neu, ltu, leu, gtu, geu, num, nan }; .BoolOp = { and, or, xor }; .type = { .b16, .b32, .b64, .u16, .u32, .u64, .s16, .s32, .s64, .f32, .f64 };

9.7.7.3. 比较和选择指令：selp

.type = { .b16, .b32, .b64, .u16, .u32, .u64, .s16, .s32, .s64, .f32, .f64 };

9.7.7.4. 比较和选择指令：slct

.dtype = { .b16, .b32, .b64, .u16, .u32, .u64, .s16, .s32, .s64, .f32, .f64 };

9.7.8. 半精度比较指令

9.7.8.1. 半精度比较指令：set

set.CmpOp.bf16.stype d, a, b; set.CmpOp.BoolOp.bf16.stype d, a, b, {!}c;

set.CmpOp{.ftz}.dtype.f16 d, a, b; set.CmpOp.BoolOp{.ftz}.dtype.f16 d, a, b, {!}c; .dtype = { .u16, .s16, .u32, .s32}

set.CmpOp.dtype.bf16 d, a, b; set.CmpOp.BoolOp.dtype.bf16 d, a, b, {!}c; .dtype = { .u16, .s16, .u32, .s32}

set.CmpOp{.ftz}.dtype.f16x2 d, a, b; set.CmpOp.BoolOp{.ftz}.dtype.f16x2 d, a, b, {!}c; .dtype = { .f16x2, .u32, .s32}

set.CmpOp.dtype.bf16x2 d, a, b; set.CmpOp.BoolOp.dtype.bf16x2 d, a, b, {!}c; .dtype = { .bf16x2, .u32, .s32}

.CmpOp = { eq, ne, lt, le, gt, ge, equ, neu, ltu, leu, gtu, geu, num, nan }; .BoolOp = { and, or, xor }; .stype = { .b16, .b32, .b64, .u16, .u32, .u64, .s16, .s32, .s64, .f16, .f32, .f64};

9.7.8.2. 半精度比较指令：setp

setp.CmpOp{.ftz}.f16x2 p|q, a, b; setp.CmpOp.BoolOp{.ftz}.f16x2 p|q, a, b, {!}c;

setp.CmpOp.bf16 p, a, b; setp.CmpOp.BoolOp.bf16 p, a, b, {!}c;

setp.CmpOp.bf16x2 p|q, a, b; setp.CmpOp.BoolOp.bf16x2 p|q, a, b, {!}c;

.CmpOp = { eq, ne, lt, le, gt, ge, equ, neu, ltu, leu, gtu, geu, num, nan }; .BoolOp = { and, or, xor };

setp.gt.or.bf16x2 u|v,c,d,s; @q setp.eq.bf16 u,j,m;

9.7.9. 逻辑与移位指令

9.7.9.1. 逻辑与移位指令：and

.type = { .pred, .b16, .b32, .b64 };

9.7.9.2. 逻辑与移位指令：or

.type = { .pred, .b16, .b32, .b64 };

9.7.9.3. 逻辑与移位指令：xor

.type = { .pred, .b16, .b32, .b64 };

9.7.9.4. 逻辑与移位指令：not

.type = { .pred, .b16, .b32, .b64 };

9.7.9.5. 逻辑与移位指令：cnot

.type = { .b16, .b32, .b64 };

9.7.9.6. 逻辑与移位指令：lop3

.BoolOp = { .or , .and };

immLut = F(ta, tb, tc);

If F = (a | b | c); immLut = 0xF0 | 0xCC | 0xAA = 0xFE

If F = (a & b & ~c); immLut = 0xF0 & 0xCC & (~0xAA) = 0x40

If F = ((a & b | c) ^ a); immLut = (0xF0 & 0xCC | 0xAA) ^ 0xF0 = 0x1A

9.7.9.7. 逻辑与移位指令：shf

.mode = { .clamp, .wrap };

// 128-bit left shift; n < 32 // [r7,r6,r5,r4] = [r3,r2,r1,r0] << n shf.l.clamp.b32 r7,r2,r3,n; shf.l.clamp.b32 r6,r1,r2,n; shf.l.clamp.b32 r5,r0,r1,n; shl.b32 r4,r0,n;

// 128-bit right shift, arithmetic; n < 32 // [r7,r6,r5,r4] = [r3,r2,r1,r0] >> n shf.r.clamp.b32 r4,r0,r1,n; shf.r.clamp.b32 r5,r1,r2,n; shf.r.clamp.b32 r6,r2,r3,n; shr.s32 r7,r3,n; // result is sign-extended

shf.r.clamp.b32 r1,r0,r0,n; // rotate right by n; n < 32 shf.l.clamp.b32 r1,r0,r0,n; // rotate left by n; n < 32

// extract 32-bits from [r1,r0] starting at position n < 32 shf.r.clamp.b32 r0,r0,r1,n;

9.7.9.8. 逻辑与移位指令：shl

.type = { .b16, .b32, .b64 };

9.7.9.9. 逻辑与移位指令：shr

.type = { .b16, .b32, .b64, .u16, .u32, .u64, .s16, .s32, .s64 };

9.7.10. 数据移动与转换指令

9.7.10.1. 缓存运算符

9.7.10.2. 缓存逐出优先级提示

9.7.10.3. 数据移动与转换指令：mov

.type = { .pred, .b16, .b32, .b64, .u16, .u32, .u64, .s16, .s32, .s64, .f32, .f64 };

9.7.10.4. 数据移动与转换指令：mov

.type = { .b16, .b32, .b64, .b128 };

// unpack 8-bit elements from .b16 { d.x, d.y } = { a[0..7], a[8..15] } // unpack 8-bit elements from .b32 { d.x, d.y, d.z, d.w } { a[0..7], a[8..15], a[16..23], a[24..31] }

// unpack 16-bit elements from .b32 { d.x, d.y } = { a[0..15], a[16..31] } // unpack 16-bit elements from .b64 { d.x, d.y, d.z, d.w } = { a[0..15], a[16..31], a[32..47], a[48..63] }

// unpack 32-bit elements from .b64 { d.x, d.y } = { a[0..31], a[32..63] }

// unpack 32-bit elements from .b128 { d.x, d.y, d.z, d.w } = { a[0..31], a[32..63], a[64..95], a[96..127] } // unpack 64-bit elements from .b128 { d.x, d.y } = { a[0..63], a[64..127] }

9.7.10.5. 数据移动与转换指令：shfl（已弃用）

.mode = { .up, .down, .bfly, .idx };

// get value of source register a if thread is active and // guard predicate true, else unpredictable if (isActive(Thread) && isGuardPredicateTrue(Thread)) { SourceA[lane] = a; } else { // Value of SourceA[lane] is unpredictable for // inactive/predicated-off threads in warp } maxLane = (lane[4:0] & mask[4:0]) | (cval[4:0] & ~mask[4:0]); minLane = (lane[4:0] & mask[4:0]);

switch (.mode) { case .up: j = lane - bval; pval = (j >= maxLane); break; case .down: j = lane + bval; pval = (j <= maxLane); break; case .bfly: j = lane ^ bval; pval = (j <= maxLane); break; case .idx: j = minLane | (bval[4:0] & ~mask[4:0]); pval = (j <= maxLane); break; } if (!pval) j = lane; // copy from own lane d = SourceA[j]; // copy input a from lane j if (dest predicate selected) p = pval;

// Warp-level INCLUSIVE PLUS REVERSE-SCAN:
//
// Assumes input in following registers:
//     - Rx  = sequence value for this thread
//
shfl.down.b32  Ry|p, Rx, 0x1,  0x1f;

@p add.f32 Rx, Ry, Rx; shfl.down.b32 Ry|p, Rx, 0x2, 0x1f; @p add.f32 Rx, Ry, Rx; shfl.down.b32 Ry|p, Rx, 0x4, 0x1f; @p add.f32 Rx, Ry, Rx; shfl.down.b32 Ry|p, Rx, 0x8, 0x1f; @p add.f32 Rx, Ry, Rx; shfl.down.b32 Ry|p, Rx, 0x10, 0x1f; @p add.f32 Rx, Ry, Rx;

// BUTTERFLY REDUCTION:
//
// Assumes input in following registers:
//     - Rx  = sequence value for this thread
//
shfl.bfly.b32  Ry, Rx, 0x10, 0x1f;   // no predicate dest
add.f32        Rx, Ry, Rx;
shfl.bfly.b32  Ry, Rx, 0x8,  0x1f;
add.f32        Rx, Ry, Rx;
shfl.bfly.b32  Ry, Rx, 0x4,  0x1f;
add.f32        Rx, Ry, Rx;
shfl.bfly.b32  Ry, Rx, 0x2,  0x1f;
add.f32        Rx, Ry, Rx;
shfl.bfly.b32  Ry, Rx, 0x1,  0x1f;
add.f32        Rx, Ry, Rx;
//
// All threads now hold sum in Rx

9.7.10.6. 数据移动与转换指令：shfl.sync

.mode = { .up, .down, .bfly, .idx };

lane[4:0] = [Thread].laneid; // position of thread in warp bval[4:0] = b[4:0]; // source lane or lane offset (0..31) cval[4:0] = c[4:0]; // clamp value segmask[4:0] = c[12:8];

// get value of source register a if thread is active and // guard predicate true, else unpredictable if (isActive(Thread) && isGuardPredicateTrue(Thread)) { SourceA[lane] = a; } else { // Value of SourceA[lane] is unpredictable for // inactive/predicated-off threads in warp } maxLane = (lane[4:0] & segmask[4:0]) | (cval[4:0] & ~segmask[4:0]); minLane = (lane[4:0] & segmask[4:0]);

switch (.mode) { case .up: j = lane - bval; pval = (j >= maxLane); break; case .down: j = lane + bval; pval = (j <= maxLane); break; case .bfly: j = lane ^ bval; pval = (j <= maxLane); break; case .idx: j = minLane | (bval[4:0] & ~segmask[4:0]); pval = (j <= maxLane); break; } if (!pval) j = lane; // copy from own lane d = SourceA[j]; // copy input a from lane j if (dest predicate selected) p = pval;

9.7.10.7. 数据移动与转换指令：prmt

.mode = { .f4e, .b4e, .rc8, .ecl, .ecr, .rc16 };

if ( ! mode ) { ctl[0] = (c >> 0) & 0xf; ctl[1] = (c >> 4) & 0xf; ctl[2] = (c >> 8) & 0xf; ctl[3] = (c >> 12) & 0xf; } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3; }

tmp[07:00] = ReadByte( mode, ctl[0], tmp64 ); tmp[15:08] = ReadByte( mode, ctl[1], tmp64 ); tmp[23:16] = ReadByte( mode, ctl[2], tmp64 ); tmp[31:24] = ReadByte( mode, ctl[3], tmp64 );

9.7.10.8. 数据移动与转换指令：ld

ld{.weak}{.ss}{.level1::eviction_priority}{.level2::eviction_priority}{.level::cache_hint}{.level::prefetch_size}{.vec}.type d, [a]{.unified}{, cache_policy};

ld.volatile{.ss}{.level::prefetch_size}{.vec}.type d, [a];

ld.relaxed.scope{.ss}{.level1::eviction_priority}{.level2::eviction_priority}{.level::cache_hint}{.level::prefetch_size}{.vec}.type d, [a]{, cache_policy};

ld.acquire.scope{.ss}{.level1::eviction_priority}{.level2::eviction_priority}{.level::cache_hint}{.level::prefetch_size}{.vec}.type d, [a]{, cache_policy};

ld.mmio.sem.sys{.global}.type d, [a];

ld{.ss}.type.proxy::readonly d, [a];

.ss = { .const, .global, .local, .param{::entry, ::func}, .shared{::cta, ::cluster} }; .cop = { .ca, .cg, .cs, .lu, .cv }; .sem = { .acquire, .relaxed }; .level1::eviction_priority = { .L1::evict_normal, .L1::evict_unchanged, .L1::evict_first, .L1::evict_last, .L1::no_allocate }; .level2::eviction_priority = {.L2::evict_normal, .L2::evict_first, .L2::evict_last}; .level::cache_hint = { .L2::cache_hint }; .level::prefetch_size = { .L2::64B, .L2::128B, .L2::256B } .scope = { .cta, .cluster, .gpu, .sys }; .vec = { .v2, .v4, .v8 }; .type = { .b8, .b16, .b32, .b64, .b128, .u8, .u16, .u32, .u64, .s8, .s16, .s32, .s64, .f32, .f64 };

ld.global.b16 %r,[fs]; // load .f16 data into 32-bit reg cvt.f32.f16 %r,%r; // up-convert f16 data to f32

ld.global.b32 %r0, [fs]; // load .f16x2 data in 32-bit reg ld.global.b32 %r1, [fs + 4]; // load .f16x2 data in 32-bit reg add.rn.f16x2 %d0, %r0, %r1; // addition of f16x2 data ld.global.relaxed.gpu.u32 %r0, [gbl]; ld.shared.acquire.gpu.u32 %r1, [sh]; ld.global.relaxed.cluster.u32 %r2, [gbl]; ld.shared::cta.acquire.gpu.u32 %r2, [sh + 4]; ld.shared::cluster.u32 %r3, [sh + 8]; ld.global.mmio.relaxed.sys.u32 %r3, [gbl]; ld.local.volatile.u32 %r4, [lcl];

ld.global.f32 d,[ugbl].unified; ld.b32 %r0, [%r1].unified;

ld.global.L1::evict_last.u32 d, [p];

ld.global.L2::64B.b32 %r0, [gbl]; // Prefetch 64B to L2 ld.L2::128B.f64 %r1, [gbl]; // Prefetch 128B to L2 ld.global.L2::256B.f64 %r2, [gbl]; // Prefetch 256B to L2

createpolicy.fractional.L2::evict_last.L2::evict_unchanged.b64 cache_policy, 1.0; ld.global.L2::cache_hint.b64 x, [p], cache_policy; ld.param::entry.b32 %rp1, [kparam1];

ld.global.b128 %r0, [gbl]; // 128-bit load

ld.global.acquire.mmio.sys.u32 %r0, [gbl];

// 256-bit load ld.global.L2::evict_last.v8.f32 { %reg0, _, %reg2, %reg3, %reg4, %reg5, %reg6, %reg7}, [addr]; ld.global.L2::evict_last.L1::evict_last.v4.u64 { %reg0, %reg1, %reg2, %reg3}, [addr];

ld.global.u32.proxy::readonly %r0, [%rd0]; ld.u32.proxy::readonly %r1, [%rd1];

9.7.10.9. 数据移动与转换指令：ld.global.nc

ld.global.nc{.level1::eviction_priority}{.level2::eviction_priority}{.level::cache_hint}{.level::prefetch_size}.type d, [a]{, cache_policy}; ld.global.nc{.level1::eviction_priority}{.level2::eviction_priority}{.level::cache_hint}{.level::prefetch_size}.vec.type d, [a]{, cache_policy};

.cop = { .ca, .cg, .cs }; // cache operation .level1::eviction_priority = { .L1::evict_normal, .L1::evict_unchanged, .L1::evict_first, .L1::evict_last, .L1::no_allocate}; .level2::eviction_priority = {.L2::evict_normal, .L2::evict_first, .L2::evict_last}; .level::cache_hint = { .L2::cache_hint }; .level::prefetch_size = { .L2::64B, .L2::128B, .L2::256B } .vec = { .v2, .v4, .v8 }; .type = { .b8, .b16, .b32, .b64, .b128, .u8, .u16, .u32, .u64, .s8, .s16, .s32, .s64, .f32, .f64 };

createpolicy.fractional.L2::evict_last.b64 cache_policy, 0.5; ld.global.nc.L2::cache_hint.f32 d, [a], cache_policy;

ld.global.nc.L2::64B.b32 d, [a]; // Prefetch 64B to L2 ld.global.nc.L2::256B.f64 d, [a]; // Prefetch 256B to L2

ld.global.nc.b128 d, [a];

ld.global.nc.L2::evict_first.v4.f64 {%reg0, %reg1. %reg2, %reg3}. [a]; // 256-bit load

9.7.10.10. 数据移动与转换指令：ldu

.ss = { .global }; // state space .vec = { .v2, .v4 }; .type = { .b8, .b16, .b32, .b64, .b128, .u8, .u16, .u32, .u64, .s8, .s16, .s32, .s64, .f32, .f64 };

9.7.10.11. 数据移动与转换指令：st

.ss = { .global, .local, .param{::func}, .shared{::cta, ::cluster} }; .sem = { .release, .relaxed }; .level1::eviction_priority = { .L1::evict_normal, .L1::evict_unchanged, .L1::evict_first, .L1::evict_last, .L1::no_allocate }; .level2::eviction_priority = { .L2::evict_normal, .L2::evict_first, .L2::evict_last }; .level::cache_hint = { .L2::cache_hint }; .cop = { .wb, .cg, .cs, .wt }; .sem = { .relaxed, .release }; .scope = { .cta, .cluster, .gpu, .sys }; .vec = { .v2, .v4, .v8 }; .type = { .b8, .b16, .b32, .b64, .b128, .u8, .u16, .u32, .u64, .s8, .s16, .s32, .s64, .f32, .f64 };

cvt.f16.f32 %r,%r; // %r is 32-bit register st.b16 [fs],%r; // store lower st.global.relaxed.sys.u32 [gbl], %r0; st.shared.release.cta.u32 [sh], %r1; st.global.relaxed.cluster.u32 [gbl], %r2; st.shared::cta.release.cta.u32 [sh + 4], %r1; st.shared::cluster.u32 [sh + 8], %r1; st.global.mmio.relaxed.sys.u32 [gbl], %r1; st.local.volatile.u32 [lcl], %r2;

st.global.L1::no_allocate.f32 [p], a;

createpolicy.fractional.L2::evict_last.b64 cache_policy, 0.25; st.global.L2::cache_hint.b32 [a], b, cache_policy;

st.param::func.b64 [param1], %rp1;

st.global.b128 [a], b; // 128-bit store

st.global.release.mmio.sys.u32 [gbl], %r0;

// 256-bit store st.global.L2::evict_last.v8.f32 [addr], { %reg0, _, %reg2, %reg3, %reg4, %reg5, %reg6, %reg7};

9.7.10.12. 数据移动与转换指令：st.async

.ss = { .shared::cluster }; .type = { .b32, .b64, .b128, .u32, .u64, .s32, .s64, .f32, .f64 }; .vec = { .v2, .v4 }; .completion_mechanism = { .mbarrier::complete_tx::bytes };

st.async{.mmio}.sem.scope{.ss}.type [a], b;

.sem = { .release }; .scope = { .gpu, .sys }; .ss = { .global }; .type = { .b8, .b16, .b32, .b64, .u8, .u16, .u32, .u64, .s8, .s16, .s32, .s64, .f32, .f64 };

st.async.sys.release.global.u32 [addr], b;

st.async.mbarrier::complete_tx::bytes.b128 [addr], b, [mbar_addr];

st.async.shared::cluster.mbarrier::complete_tx::bytes.b128 [addr], b, [mbar_addr];

9.7.10.13. 数据移动与转换指令：multimem.st.async

.sem = { .release }; .scope = { .gpu, .sys }; .ss = { .global }; .type = { .b8, .b16, .b32, .b64, .u8, .u16, .u32, .u64, .s8, .s16, .s32, .s64, .f32, .f64 };

// Release store, system scope, generic addressing for multimem operand. multimem.st.async.release.sys.f64 [mm_addr], src_f64;

9.7.10.14. 数据移动与转换指令：st.bulk

st.bulk [gdst], 4096, 0;

9.7.10.15. 数据移动与转换指令：multimem.ld_reduce 、 multimem.st 、 multimem.red

multimem.ld_reduce{.ldsem}{.scope}{.ss}.op.type d, [a]; multimem.ld_reduce.weak{.ss}.op.type d, [a];

multimem.st{.stsem}{.scope}{.ss}.type [a], b; multimem.st.weak{.ss}.type [a], b;

multimem.red{.redsem}{.scope}{.ss}.op.type [a], b;

.ss = { .global } .ldsem = { .relaxed, .acquire } .stsem = { .relaxed, .release } .redsem = { .relaxed, .release } .scope = { .cta, .cluster, .gpu, .sys } .op = { .min, .max, .add, .and, .or, .xor } .type = { .b32, .b64, .u32, .u64, .s32, .s64 }

// Floating point type:

multimem.ld_reduce{.ldsem}{.scope}{.ss}.op{.acc_prec}{.vec}.type d, [a]; multimem.ld_reduce.weak{.ss}.op{.acc_prec}{.vec}.type d, [a];

multimem.st{.stsem}{.scope}{.ss}{.vec}.type [a], b; multimem.st.weak{.ss}{.vec}.type [a], b;

multimem.red{.redsem}{.scope}{.ss}.redop{.vec}.redtype [a], b;

.ss = { .global } .ldsem = { .relaxed, .acquire } .stsem = { .relaxed, .release } .redsem = { .relaxed, .release } .scope = { .cta, .cluster, .gpu, .sys } .op = { .min, .max, .add } .redop = { .add } .acc_prec = { .acc::f32, .acc::f16 } .vec = { .v2, .v4, .v8 } .type= { .f16, .f16x2, .bf16, .bf16x2, .f32, .f64, .e5m2, .e5m2x2, .e5m2x4, .e4m3, .e4m3x2, .e4m3x4 } .redtype = { .f16, .f16x2, .bf16, .bf16x2, .f32, .f64 }

multimem.st.relaxed.gpu.b32 [addr3], val3_b32; multimem.st.release.cta.global.u32 [addr4], val4_u32;

multimem.red.relaxed.gpu.max.f64 [addr5], val5_f64; multimem.red.release.cta.global.add.v4.f32 [addr6], {val6, val7, val8, val9}; multimem.ld_reduce.add.acc::f32.v2.f16x2 {val_10, val_11}, [addr7];

multimem.ld_reduce.relaxed.cta.min.v2.e4m3x2 {val_12, val_13}, [addr8]; multimem.ld_reduce.relaxed.cta.add.v4.e4m3 {val_14, val_15, val_16, val_17}, [addr9]; multimem.ld_reduce.add.acc::f16.v4.e5m2 {val_18, val_19, val_20, val_21}, [addr10];

9.7.10.16. 数据移动与转换指令：prefetch 、 prefetchu

prefetchu.L1 [a]; // prefetch to uniform cache

prefetch{.tensormap_space}.tensormap [a]; // prefetch the tensormap

.space = { .global, .local }; .level = { .L1, .L2 }; .level::prefetch_size = { .L1::32B }; .level::eviction_priority = { .L2::evict_last, .L2::evict_normal }; .tensormap_space = { .const, .param };

9.7.10.17. 数据移动与转换指令：applypriority

.level::eviction_priority = { .L2::evict_normal };

9.7.10.18. 数据移动与转换指令：applypriority.async.bulk

.level::eviction_priority = { .L2::evict_normal }; .src = { .global }; .completion_mechanism = { .bulk_group };

9.7.10.19. 数据移动与转换指令：applypriority.async.bulk.tensor

.dim = { .1d, .2d, .3d, .4d, .5d }; .level::eviction_priority = { .L2::evict_normal }; .src = { .global }; .override_attribute = { .override::global_dim_stride, .override::global_dim }; .completion_mechanism = { .bulk_group }; .load_mode = { .tile, .tile::gather4, .im2col, .im2col::w, .im2col::w::128 };

9.7.10.20. 数据移动与转换指令：discard

.level = { .L2 };

9.7.10.21. 数据移动与转换指令：createpolicy

// Fabric range-based policy createpolicy.range.fabric.level::primary_priority{.level::secondary_priority}.b64 cache_policy, [aLe, aOff], primary-size, total-size;

// Fraction-based policy createpolicy.fractional.level::primary_priority{.level::secondary_priority}.b64 cache_policy{, fraction};

// Converting the access property from CUDA APIs createpolicy.cvt.L2.b64 cache_policy, access-property;

.level::primary_priority = { .L2::evict_last, .L2::evict_normal, .L2::evict_first, .L2::evict_unchanged }; .level::secondary_priority = { .L2::evict_first, .L2::evict_unchanged };

createpolicy.range.L2::evict_last.L2::evict_first.b64 policy, [ptr], 0x100000, 0x200000;

createpolicy.range.fabric.L2::evict_last.L2::evict_first.b64 policy, [leid, off], 0x100000, 0x200000;

// access-prop is created by CUDA APIs. createpolicy.cvt.L2.b64 policy, access-prop;

9.7.10.22. 数据移动与转换指令：isspacep

.space = { const, .global, .local, .shared{::cta, ::cluster}, .param{::entry} };

9.7.10.23. 数据移动与转换指令：cvta

// convert generic address to const, global, local, or shared address cvta.to.space.size p, a;

.space = { .const, .global, .local, .shared{::cta, ::cluster}, .param{::entry} }; .size = { .u32, .u64 };

9.7.10.24. 数据移动与转换指令：cvt

cvt.frnd2{.relu}{.satfinite}{.pzo}.f16.f32 d, a; cvt.frnd2{.relu}{.satfinite}{.pzo}.f16x2.f32 d, a, b; cvt.rs{.relu}{.satfinite}.f16x2.f32 d, a, b, rbits;

cvt.frnd2{.relu}{.satfinite}{.pzo}.bf16.f32 d, a; cvt.frnd2{.relu}{.satfinite}{.pzo}.bf16x2.f32 d, a, b; cvt.rs{.relu}{.satfinite}.bf16x2.f32 d, a, b, rbits;

cvt.rna{.satfinite}.tf32.f32 d, a; cvt.frnd2{.satfinite}{.relu}{.pzo}.tf32.f32 d, a;

cvt.frnd2.satfinite{.relu}{.pzo}{.scaled::n1::ue8m0}.f8x2type.f32 d, a, b{, scale-factor}; cvt.frnd2.satfinite{.relu}{.pzo}{.scaled::n1::ue8m0}.f8x2type.fp16x2 d, a{, scale-factor}; cvt.rn{.relu}.f16x2.f8x2type d, a; cvt.rn{.relu}{.satfinite}{.scaled::n2::ue8m0}.bf16x2.f8x2type d, a{, scale-factor}; cvt.rs{.relu}.satfinite.f8x4type.f32 d, {a, b, e, f}, rbits;

cvt.frnd2.satfinite{.relu}{.pzo}{.scaled::n1::ue8m0}.f4x2type.f32 d, a, b{, scale-factor}; cvt.frnd2.satfinite{.relu}{.pzo}{.scaled::n1::ue8m0}.f4x2type.fp16x2type d, a{, scale-factor}; cvt.rn{.relu}.f16x2.f4x2type d, a; cvt.rn{.relu}{.satfinite}{.scaled::n2::ue8m0}.bf16x2.f4x2type d, a{, scale-factor}; cvt.rs{.relu}.satfinite.f4x4type.f32 d, {a, b, e, f}, rbits;

cvt.frnd2.satfinite{.relu}{.pzo}{.scaled::n1::ue8m0}.f6x2type.f32 d, a, b{, scale-factor}; cvt.frnd2.satfinite{.relu}{.pzo}{.scaled::n1::ue8m0}.f6x2type.fp16x2type d, a{, scale-factor}; cvt.rn{.relu}.f16x2.f6x2type d, a; cvt.rn{.relu}{.satfinite}{.scaled::n2::ue8m0}.bf16x2.f6x2type d, a{, scale-factor}; cvt.rs{.relu}.satfinite.f6x4type.f32 d, {a, b, e, f}, rbits;

cvt.frnd3{.satfinite}.ue8m0x2.f32 d, a, b; cvt.frnd3{.satfinite}.ue8m0x2.bf16x2 d, a; cvt.rn.bf16x2.ue8m0x2 d, a;

cvt.frnd2.satfinite{.relu}{.scaled::n2::ue8m0}.s2f6x2.f32 d, a, b{, scale-factor}; cvt.frnd2.satfinite{.relu}{.scaled::n2::ue8m0}.s2f6x2.bf16x2 d, a{, scale-factor}; cvt.rn{.satfinite}{.relu}{.scaled::n2::ue8m0}.bf16x2.s2f6x2 d, a{, scale-factor};

cvt.frnd4{.satfinite}.ue5m3x2.f32 d, a, b; cvt.frnd2{.satfinite}.scaled::n1::ue8m0.ue5m3x2.f32 d, a, b, scale-factor;

cvt.frnd4{.satfinite}.ue5m3x2.fp16x2type d, a; cvt.frnd2{.satfinite}.scaled::n1::ue8m0.ue5m3x2.fp16x2type d, a, scale-factor;

cvt.rn.f16x2.ue5m3x2 d, a; cvt.rn{.satfinite}{.scaled::n2::ue8m0}.bf16x2.ue5m3x2 d, a{, scale-factor};

.irnd = { .rni, .rzi, .rmi, .rpi }; .frnd = { .rn, .rz, .rm, .rp }; .frnd2 = { .rn, .rz }; .frnd3 = { .rz, .rp }; .frnd4 = { .rn, .rz, .rp }; .dtype = .atype = { .u8, .u16, .u32, .u64, .s8, .s16, .s32, .s64, .bf16, .f16, .f32, .f64 }; .f8x2type = { .e4m3x2, .e5m2x2 }; .f4x2type = { .e2m1x2 }; .f6x2type = { .e2m3x2, .e3m2x2 }; .f4x4type = { .e2m1x4 }; .f8x4type = { .e4m3x4, .e5m2x4 }; .f6x4type = { .e2m3x4, .e3m2x4 }; .fp16x2type = { .f16x2, .bf16x2 };

cvt.rs.f16x2.f32 d, a, b, rbits; // convert 2 fp32 values to packed fp16 with applying .rs rounding cvt.rs.satfinite.e2m1x4.f32 d, {a, b, e, f}, rbits; // convert 4 fp32 values to packed 4 e2m1 values with applying .rs rounding

cvt.rn.satfinite.relu.e2m1x2.f16x2 d, a; // unpack a and convert to two .e2m1 values cvt.rn.satfinite.e2m3x2.bf16x2 d, a; // unpack a and convert to two .e2m3 values

// Convert 2 f32 values to s2f6 after applying scale factor for dividing the value cvt.rn.satfinite.scaled::n2::ue8m0.s2f6x2.f32 d, a, b, scale-factor;

cvt.rz.satfinite.e2m3x2.f32 d, a, b; // convert a, b to .e2m3 and pack as .e2m3x2 with round towards zero mode

cvt.rn.bf16.f32.pzo b, f; // convert fp32 to bf16 with positive zero's only

cvt.rn.relu.satfinite.f16x2.f32.pzo b1, f, f1; // convert two fp32 values to packed fp16 outputs with .relu saturation on each output and produce positive zero's only

cvt.rn.satfinite.scaled::n1::ue8m0.e4m3x2.bf16x2 b16_0, b32_0, b8_0;

cvt.bf16x2.e5m2x2.rn.relu.scaled::n2::ue8m0.satfinite d, a, scale-factor;

9.7.10.25. 数据移动与转换指令：cvt.pack

cvt.pack.sat.convertType.abType.cType d, a, b, c; .convertType = { .u2, .s2, .u4, .s4, .u8, .s8 } .abType = { .s32 } .cType = { .b32 }

size = sizeInBits(convertType); td = tb ; for (i = size; i <= 2 * size - 1; i++) { td[i] = ta[i - size]; }

if (isU16(convertType) || isS16(convertType)) { d = td; } else { for (i = 0; i < 2 * size; i++) { d[i] = td[i]; } for (i = 2 * size; i <= 31; i++) { d[i] = c[i - 2 * size]; } }

9.7.10.26. 数据移动与转换指令：mapa

// Maps shared memory address in register a into CTA b. mapa.shared::cluster.type d, a, b;

// Maps shared memory variable into CTA b. mapa.shared::cluster.type d, sh, b;

// Maps shared memory variable into CTA b. mapa.shared::cluster.type d, sh + imm, b;

// Maps generic address in register a into CTA b. mapa.type d, a, b;

.space = { .shared::cluster } .type = { .u32, .u64 }

9.7.10.27. 数据移动与转换指令：getctarank

// Get cta rank from source shared memory address in register a. getctarank.shared::cluster.type d, a;

// Get cta rank from shared memory variable. getctarank.shared::cluster.type d, var;

// Get cta rank from shared memory variable+offset. getctarank.shared::cluster.type d, var + imm;

// Get cta rank from generic address of shared memory variable in register a. getctarank.type d, a;

.space = { .shared::cluster } .type = { .u32, .u64 }

9.7.10.28. 数据移动与转换指令：异步拷贝

9.7.10.28.1. 异步拷贝操作的完成机制

9.7.10.28.1.1. 异步组机制

9.7.10.28.1.2. 基于 mbarrier 的机制

9.7.10.28.1.3. 异步拷贝操作的报告机制

9.7.10.28.2. 异步代理

9.7.10.28.3. 数据移动与转换指令：非批量拷贝

9.7.10.28.3.1. 数据移动与转换指令：cp.async

.level::cache_hint = { .L2::cache_hint } .level::prefetch_size = { .L2::64B, .L2::128B, .L2::256B } cp-size = { 4, 8, 16 }

cp.async.cg.shared.global.L2::64B [%r2], [%r3], 16; cp.async.cg.shared.global.L2::128B [%r0 + 16], [%r1], 16; cp.async.cg.shared.global.L2::256B [%r2 + 32], [%r3], 16;

createpolicy.fractional.L2::evict_last.L2::evict_unchanged.b64 cache_policy, 0.25; cp.async.ca.shared.global.L2::cache_hint [%r2], [%r1], 4, cache_policy;

cp.async.ca.shared.global [shrd], [gbl], 4, p; cp.async.cg.shared.global.L2::cache_hint [%r0], [%r2], 16, q, cache_policy;

9.7.10.28.3.2. 数据移动与转换指令：cp.async.commit_group

// Example 2: cp.async.ca.shared.global [shrd1], [gbl1], 8; cp.async.ca.shared.global [shrd1+8], [gbl1+8], 8; cp.async.commit_group ; // Marks the end of cp.async group 1

cp.async.ca.shared.global [shrd2], [gbl2], 16; cp.async.cg.shared.global [shrd2+16], [gbl2+16], 16; cp.async.commit_group ; // Marks the end of cp.async group 2

9.7.10.28.3.3. 数据移动与转换指令：cp.async.wait_group / cp.async.wait_all

// Example of .wait_group : cp.async.ca.shared.global [shrd3], [gbl3], 8; cp.async.commit_group; // End of group 1

cp.async.cg.shared.global [shrd4], [gbl4], 16; cp.async.commit_group; // End of group 2

cp.async.cg.shared.global [shrd5], [gbl5], 16; cp.async.commit_group; // End of group 3

cp.async.wait_group 1; // waits for group 1 and group 2 to complete

9.7.10.28.4. 数据移动与转换指令：批量拷贝

9.7.10.28.4.1. 数据移动与转换指令：cp.async.bulk

.sem = { .weak } .dst = { .shared::cta } .src = { .global } .completion_mechanism = { .mbarrier::complete_tx::bytes{.report_mechanism} } .level::cache_hint = { .L2::cache_hint } .report_mechanism = { .mbarrier::report::disabled, .mbarrier::report::validity::per_16bytes::80000000, .mbarrier::report::validity::per_16bytes::8000, .mbarrier::report::validity::per_16bytes::80, .mbarrier::report::validity::per_16bytes::8, .mbarrier::report::validity::per_element::ff }

cp.async.bulk.sem.scope.dst.src.completion_mechanism{.level::cache_hint}{.ignore_oob}.type [dstMem], [srcMem], size{, ignoreBytesLeft, ignoreBytesRight}, [mbar] {, cache_policy};

.sem = { .relaxed } .scope = { .cta, .cluster, .gpu, .sys } .dst = { .shared::cta } .src = { .global } .completion_mechanism = { .mbarrier::complete_tx::bytes{.report_mechanism} } .level::cache_hint = { .L2::cache_hint } .type = { .b128 } .report_mechanism = { .mbarrier::report::disabled, .mbarrier::report::validity::per_16bytes::80000000, .mbarrier::report::validity::per_16bytes::8000, .mbarrier::report::validity::per_16bytes::80, .mbarrier::report::validity::per_16bytes::8, .mbarrier::report::validity::per_element::ff }

// global -> shared::cluster cp.async.bulk{.sem}.dst.src.completion_mechanism{.multicast}{.level::cache_hint} [dstMem], [srcMem], size, [mbar] {, ctaMask} {, cache_policy}

.sem = { .weak } .dst = { .shared::cluster } .src = { .global } .completion_mechanism = { .mbarrier::complete_tx::bytes{.report_mechanism} } .level::cache_hint = { .L2::cache_hint } .multicast = { .multicast::cluster{::16b, ::32b} } .report_mechanism = { .mbarrier::report::disabled, .mbarrier::report::validity::per_16bytes::80000000, .mbarrier::report::validity::per_16bytes::8000, .mbarrier::report::validity::per_16bytes::80, .mbarrier::report::validity::per_16bytes::8, .mbarrier::report::validity::per_element::ff }

cp.async.bulk.sem.scope.dst.src.completion_mechanism{.multicast}{.level::cache_hint}.type [dstMem], [srcMem], size, [mbar] {, ctaMask} {, cache_policy};

.sem = { .relaxed } .scope = { .cta, .cluster, .gpu, .sys } .dst = { .shared::cluster } .src = { .global } .completion_mechanism = { .mbarrier::complete_tx::bytes{.report_mechanism} } .level::cache_hint = { .L2::cache_hint } .type = { .b128 } .multicast = { .multicast::cluster{::16b, ::32b} } .report_mechanism = { .mbarrier::report::disabled, .mbarrier::report::validity::per_16bytes::80000000, .mbarrier::report::validity::per_16bytes::8000, .mbarrier::report::validity::per_16bytes::80, .mbarrier::report::validity::per_16bytes::8, .mbarrier::report::validity::per_element::ff }

// shared::cta -> shared::cluster cp.async.bulk{.sem}.dst.src.completion_mechanism [dstMem], [srcMem], size, [mbar]

.sem = { .weak } .dst = { .shared::cluster } .src = { .shared::cta } .completion_mechanism = { .mbarrier::complete_tx::bytes }

cp.async.bulk.sem.scope.dst.src.completion_mechanism.type [dstMem], [srcMem], size, [mbar];

.sem = { .relaxed } .scope = { .cta, .cluster } .dst = { .shared::cluster } .src = { .shared::cta } .completion_mechanism = { .mbarrier::complete_tx::bytes } .type = { .b128 }

// shared::cta -> global cp.async.bulk{.sem}.dst.src.completion_mechanism{.level::cache_hint}{.cp_mask} [dstMem], [srcMem], size {, cache_policy} {, byteMask}

.sem = { .weak } .dst = { .global } .src = { .shared::cta } .completion_mechanism = { .bulk_group } .level::cache_hint = { .L2::cache_hint }

cp.async.bulk.sem.scope.dst.src.completion_mechanism{.level::cache_hint}{.cp_mask}.type [dstMem], [srcMem], size {, cache_policy} {, byteMask};

cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes.L2::cache_hint [dstMem], [srcMem], size, [mbar], cache_policy;

// .global -> .shared::cluster: cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [mbar];

cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::cluster [dstMem], [srcMem], size, [mbar], ctaMask;

cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes.L2::cache_hint [dstMem], [srcMem], size, [mbar], cache_policy;

cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::cluster::32b [dstMem], [srcMem], size, [mbar], ctaMask32;

// Validity check using 0x8000 pattern on every 16B cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes.mbarrier::report::validity::per_16bytes::8000 [dstMem], [srcMem], size, [mbar];

// .shared::cta -> .shared::cluster (strictly remote): cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes [dstMem], [srcMem], size, [mbar];

// .shared::cta -> .global: cp.async.bulk.global.shared::cta.bulk_group [dstMem], [srcMem], size;

cp.async.bulk.global.shared::cta.bulk_group.L2::cache_hint} [dstMem], [srcMem], size, cache_policy;

// .shared::cta -> .global with .cp_mask: cp.async.bulk.global.shared::cta.bulk_group.L2::cache_hint.cp_mask [dstMem], [srcMem], size, cache_policy, byteMask;

// ignore_oob cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes.ignore_oob [dstMem], [srcMem], size, ignoreBytesLeft, ignoreBytesRight, [mbar];

// .global -> .shared::cta with .relaxed scope and .b128 type cp.async.bulk.relaxed.shared::cta.global.mbarrier::complete_tx::bytes.b128 [dstMem], [srcMem], size, [mbar];

cp.async.bulk.relaxed.shared::cta.global.mbarrier::complete_tx::bytes.L2::cache_hint.b128 [dstMem], [srcMem], size, [mbar], cache_policy;

9.7.10.28.4.2. 数据移动与转换指令：cp.reduce.async.bulk

.sem = { .relaxed } .scope = { .cta, .cluster } .dst = { .shared::cluster } .src = { .shared::cta } .completion_mechanism = { .mbarrier::complete_tx::bytes } .redOp= { .and, .or, .xor, .add, .inc, .dec, .min, .max } .type = { .b32, .u32, .s32, .b64, .u64 }

cp.reduce.async.bulk{.sem.scope}.dst.src.completion_mechanism{.level::cache_hint}.redOp.type [dstMem], [srcMem], size{, cache_policy}

.sem = { .relaxed } .scope = { .cta, .cluster, .gpu, .sys } .dst = { .global } .src = { .shared::cta } .completion_mechanism = { .bulk_group } .level::cache_hint = { .L2::cache_hint } .redOp= { .and, .or, .xor, .add, .inc, .dec, .min, .max } .type = { .f16, .bf16, .b32, .u32, .s32, .b64, .u64, .s64, .f32, .f64 }

cp.reduce.async.bulk{.sem.scope}.dst.src.completion_mechanism{.level::cache_hint}.add.noftz.type [dstMem], [srcMem], size{, cache_policy}

.sem = { .relaxed } .scope = { .cta, .cluster, .gpu, .sys } .dst = { .global } .src = { .shared::cta } .completion_mechanism = { .bulk_group } .type = { .f16, .bf16, .f32 }

cp.reduce.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes.min.s32 [dstMem], [srcMem], size, [mbar];

cp.reduce.async.bulk.global.shared::cta.bulk_group.min.f16 [dstMem], [srcMem], size;

cp.reduce.async.bulk.global.shared::cta.bulk_group.L2::cache_hint.xor.s32 [dstMem], [srcMem], size, policy;

cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.f16 [dstMem], [srcMem], size;

cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.f32 [dstMem], [srcMem], size;

cp.reduce.async.bulk.relaxed.cta.global.bulk_group.add.u64 [dstMem], [srcMem], size, [mbar];

9.7.10.28.4.3. 数据移动与转换指令：cp.async.bulk.prefetch

.src = { .global } .level::cache_hint = { .L2::cache_hint } .level::eviction_priority = { .L2::evict_last }

cp.async.bulk.prefetch.L2.global.L2::cache_hint [srcMem], size, policy;

cp.async.bulk.prefetch.L2.global.L2::evict_last [srcMem], size;

9.7.10.28.4.4. 数据移动与转换指令：multimem.cp.async.bulk

.sem                  = { .weak }
.dst                  = { .global }
.src                  = { .shared::cta }
.completion_mechanism = { .bulk_group }

multimem.cp.async.bulk.sem.scope.dst.src.completion_mechanism{.cp_mask}.type [dstMem], [srcMem], size{, byteMask};

.sem                  = { .relaxed }
.scope                = { .cta, .cluster, .gpu, .sys }
.dst                  = { .global }
.src                  = { .shared::cta }
.completion_mechanism = { .bulk_group }
.type                 = { .b128 }

multimem.cp.async.bulk.global.shared::cta.bulk_group [dstMem], [srcMem], 512;

multimem.cp.async.bulk.global.shared::cta.bulk_group.cp_mask [dstMem], [srcMem], size, byteMask;

multimem.cp.async.bulk.relaxed.cta.global.bulk_group.b128 [dstMem], [srcMem], size;

9.7.10.28.4.5. 数据移动与转换指令：multimem.cp.reduce.async.bulk

.sem                  =  { .relaxed }
.scope                = { .cta, .cluster, .gpu, .sys }
.dst                  = { .global }
.src                  = { .shared::cta }
.completion_mechanism = { .bulk_group }
.redOp                = { .and, .or, .xor,
                          .add, .inc, .dec,
                          .min, .max }
.type                 = { .f16, .bf16,
                          .b32, .u32, .s32,
                          .b64, .u64, .s64,
                          .f32, .f64 }

multimem.cp.reduce.async.bulk{.sem.scope}.dst.src.completion_mechanism.add.noftz.type [dstMem], [srcMem], size;

.sem                  = { .relaxed }
.scope                = { .cta, .cluster, .gpu, .sys }
.dst                  = { .global }
.src                  = { .shared::cta }
.completion_mechanism = { .bulk_group }
.type                 = { .f16, .bf16, .f32 }

multimem.cp.reduce.async.bulk.global.shared::cta.bulk_group.xor.b64 [dstMem], [srcMem], size;

multimem.cp.reduce.async.bulk.global.shared::cta.bulk_group.inc.u32 [dstMem], [srcMem], size;

multimem.cp.reduce.async.bulk.global.shared::cta.bulk_group.dec.u32 [dstMem], [srcMem], size;

multimem.cp.reduce.async.bulk.global.shared::cta.bulk_group.max.s32 [dstMem], [srcMem], size;

multimem.cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.f16 [dstMem], [srcMem], size;

multimem.cp.reduce.async.bulk.global.shared::cta.bulk_group.min.bf16 [dstMem], [srcMem], size;

multimem.cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.bf16 [dstMem], [srcMem], size;

multimem.cp.reduce.async.bulk.global.shared::cta.bulk_group.add.noftz.f32 [dstMem], [srcMem], size;

multimem.cp.reduce.async.bulk.relaxed.cta.global.bulk_group.add.u64 [dstMem], [srcMem], size, [mbar];

9.7.10.28.5. 数据移动与转换指令：张量拷贝

9.7.10.28.5.1. 张量拷贝指令的限制

9.7.10.28.5.2. 覆盖张量属性值

9.7.10.28.5.2.1. 张量基地址覆盖

9.7.10.28.5.2.2. 张量属性覆盖

9.7.10.28.5.3. 数据移动与转换指令：cp.async.bulk.tensor

.dst = { .shared::cta } .src = { .global } .dim = { .1d, .2d, .3d, .4d, .5d } .completion_mechanism = { .mbarrier::complete_tx::bytes{.report_mechanism} } .cta_group = { .cta_group::1, .cta_group::2 } .load_mode = { .tile, .tile::gather4, .im2col, .im2col::w, .im2col::w::128 } .level::cache_hint = { .L2::cache_hint } .override_attribute = { .override::global_dim, .override::global_dim_stride } .report_mechanism = { .mbarrier::report::disabled, .mbarrier::report::validity::per_16bytes::80000000, .mbarrier::report::validity::per_16bytes::8000, .mbarrier::report::validity::per_16bytes::80, .mbarrier::report::validity::per_16bytes::8, .mbarrier::report::validity::per_element::ff }

// global -> shared::cluster cp.async.bulk.tensor.dim.dst.src{.load_mode}.completion_mechanism{.multicast}{.cta_group}{.level::cache_hint}{.override::global_address}{.override_attribute} [dstMem], [tensorMap{, gAddrToOverride}{, attributeOverrideInfo}, tensorCoords], [mbar]{, im2colInfo} {, ctaMask} {, cache_policy}

.dst = { .shared::cluster } .src = { .global } .dim = { .1d, .2d, .3d, .4d, .5d } .completion_mechanism = { .mbarrier::complete_tx::bytes{.report_mechanism} } .cta_group = { .cta_group::1, .cta_group::2 } .load_mode = { .tile, .tile::gather4, .im2col, .im2col::w, .im2col::w::128 } .level::cache_hint = { .L2::cache_hint } .multicast = { .multicast::cluster{::16b, ::32b} } .override_attribute = { .override::global_dim, .override::global_dim_stride } .report_mechanism = { .mbarrier::report::disabled, .mbarrier::report::validity::per_16bytes::80000000, .mbarrier::report::validity::per_16bytes::8000, .mbarrier::report::validity::per_16bytes::80, .mbarrier::report::validity::per_16bytes::8, .mbarrier::report::validity::per_element::ff }

// shared::cta -> global cp.async.bulk.tensor.dim.dst.src{.load_mode}.completion_mechanism{.level::cache_hint}{.override::global_address}{.override_attribute} [tensorMap{, gAddrToOverride}{, attributeOverrideInfo}, tensorCoords], [srcMem] {, cache_policy}

.dst = { .global } .src = { .shared::cta } .dim = { .1d, .2d, .3d, .4d, .5d } .completion_mechanism = { .bulk_group } .load_mode = { .tile, .tile::scatter4, .im2col_no_offs, .im2col_no_offs::w } .level::cache_hint = { .L2::cache_hint } .override_attribute = { .override::global_dim, .override::global_dim_stride }

cp.async.bulk.tensor.1d.shared::cta.global.mbarrier::complete_tx::bytes.tile [sMem0], [tensorMap0, {tc0}], [mbar0];

@p cp.async.bulk.tensor.5d.shared::cta.global.im2col.mbarrier::complete_tx::bytes [sMem2], [tensorMap2, {tc0, tc1, tc2, tc3, tc4}], [mbar2], {i2cOffW, i2cOffH, i2cOffD};

cp.async.bulk.tensor.1d.shared::cluster.global.mbarrier::complete_tx::bytes.tile [sMem0], [tensorMap0, {tc0}], [mbar0];

@p cp.async.bulk.tensor.2d.shared::cluster.global.mbarrier::complete_tx::bytes.multicast::cluster [sMem1], [tensorMap1, {tc0, tc1}], [mbar2], ctaMask;

@p cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes [sMem2], [tensorMap2, {tc0, tc1, tc2, tc3, tc4}], [mbar2], {i2cOffW, i2cOffH, i2cOffD};

@p cp.async.bulk.tensor.3d.im2col.shared::cluster.global.mbarrier::complete_tx::bytes.L2::cache_hint [sMem3], [tensorMap3, {tc0, tc1, tc2}], [mbar3], {i2cOffW}, policy;

@p cp.async.bulk.tensor.1d.global.shared::cta.bulk_group [tensorMap3, {tc0}], [sMem3];

cp.async.bulk.tensor.2d.tile::gather4.shared::cluster.global.mbarrier::complete_tx::bytes [sMem5], [tensorMap6, {x0, y0, y1, y2, y3}], [mbar5];

cp.async.bulk.tensor.3d.im2col::w.shared::cluster.global.mbarrier::complete_tx::bytes [sMem4], [tensorMap5, {t0, t1, t2}], [mbar4], {im2colwHalo, im2colOff};

cp.async.bulk.tensor.1d.shared::cluster.global.tile.cta_group::2 [sMem6], [tensorMap7, {tc0}], [peerMbar];

cp.async.bulk.tensor.mbarrier::complete_tx::bytes.shared::cta.global.1d.override::global_address [sMem7], [tensorMap8, gAddrToOverride1, {tc0}], [peerMbar];

cp.async.bulk.tensor.mbarrier::complete_tx::bytes.shared::cta.global.5d.tile.override::global_address.cta_group::1.override::global_dim_stride [sMem8], [tensorMap9, gAddrToOverride2, {newTensorSize_0, newTensorSize_1, newTensorSize_2, newTensorSize_3, newTensorSize_4}, {newTensorLowerStrd_0, newTensorLowerStrd_1, newTensorLowerStrd_2, newTensorLowerStrd_3}, tensorUpperStrd, {0, 0, 0, 0, 0}], [mbar];

cp.async.bulk.tensor.global.shared::cta.1d.bulk_group.tile.override::global_address.override::global_dim [tensorMap10, gAddrToOverride3, {newTensorSize_0}, {0}], [sMem9];

cp.async.bulk.tensor.mbarrier::complete_tx::bytes.shared::cluster.global.4d.im2col::w::128.override::global_address.cta_group::1 [sMem10], [tensorMap11, gAddrToOverride4, {tc0, tc1, tc2, tc3}], [mbar5], {im2col_0, im2col_1};

cp.async.bulk.tensor.3d.global.shared::cta.bulk_group.im2col_no_offs::w [tensorMap6, {tc0, tc1, tc2}], [sMem11];

// Validity check using 0x8 pattern on every 16B cp.async.bulk.tensor.1d.shared::cluster.global.mbarrier::complete_tx::bytes.mbarrier::report::validity::per_16bytes::8 [sMem], [tensorDesc, {u}], [mbar];

// Validity check using 0xff pattern on per element cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.mbarrier::report::validity::per_element::ff [sMem], [tensorDesc, {u, v, w, x, y}], [mbar];

9.7.10.28.5.4. 数据移动与转换指令：cp.reduce.async.bulk.tensor

.dst = { .global } .src = { .shared::cta } .dim = { .1d, .2d, .3d, .4d, .5d } .completion_mechanism = { .bulk_group } .load_mode = { .tile, .im2col_no_offs, .im2col_no_offs::w } .redOp = { .add, .min, .max, .inc, .dec, .and, .or, .xor} .override_attribute = { .override::global_dim, .override::global_dim_stride }

cp.reduce.async.bulk.tensor.1d.global.shared::cta.add.tile.bulk_group [tensorMap0, {tc0}], [sMem0];

cp.reduce.async.bulk.tensor.2d.global.shared::cta.and.bulk_group.L2::cache_hint [tensorMap1, {tc0, tc1}], [sMem1] , policy;

cp.reduce.async.bulk.tensor.3d.global.shared::cta.xor.im2col.bulk_group [tensorMap2, {tc0, tc1, tc2}], [sMem2];

cp.reduce.async.bulk.tensor.global.shared::cta.bulk_group.2d.tile.min.override::global_address [tensorMap3, gAddrToOverride1, {tc0, tc1}], [sMem3];

cp.reduce.async.bulk.tensor.global.shared::cta.bulk_group.1d.max.L2::cache_hint.override::global_address.override::global_dim [tensorMap4, gAddrToOverride2, {newTensorSize_0}, {0}], [sMem4], policy;

cp.reduce.async.bulk.tensor.3d.global.shared::cta.or.im2col_no_offs::w.bulk_group [tensorMap5, {tc0, tc1, tc2}], [sMem5];

9.7.10.28.5.5. 数据移动与转换指令：cp.async.bulk.prefetch.tensor

cp.async.bulk.prefetch.tensor.dim.L2.src{.load_mode}{.level::eviction_priority}{.override::global_address}{.override_attribute} [tensorMap{, gAddrToOverride}{, attributeOverrideInfo}, tensorCoords] {, im2colInfo }

.src = { .global } .dim = { .1d, .2d, .3d, .4d, .5d } .load_mode = { .tile, .tile::gather4, .im2col, .im2col::w, .im2col::w::128 } .level::cache_hint = { .L2::cache_hint } .level::eviction_priority = { .L2::evict_last } .override_attribute = { .override::global_dim, .override::global_dim_stride }

cp.async.bulk.prefetch.tensor.1d.L2.global.tile [tensorMap0, {tc0}];

@p cp.async.bulk.prefetch.tensor.2d.L2.global [tensorMap1, {tc0, tc1}];

@p cp.async.bulk.prefetch.tensor.5d.L2.global.im2col [tensorMap2, {tc0, tc1, tc2, tc3, tc4}], {i2cOffW, i2cOffH, i2cOffD};

@p cp.async.bulk.prefetch.tensor.3d.L2.global.im2col.L2::cache_hint [tensorMap3, {tc0, tc1, tc2}], {i2cOffW}, policy;

cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4 [tensorMap5, {col_idx, row_idx0, row_idx1, row_idx2, row_idx3}];

cp.async.bulk.prefetch.tensor.4d.L2.global.im2col::w::128 [tensorMap4, {t0, t1, t2, t3}], {im2colwHalo, im2colOff};

cp.async.bulk.prefetch.tensor.3d.L2.global.tile::gather4.L2::evict_last [tensorMap5, {t0, t1, t2}], {i2cOffW};

cp.async.bulk.prefetch.tensor.2d.L2.global.tile.override::global_address [tensorMap6, gAddrToOverride1, {t0, t1}];

cp.async.bulk.prefetch.tensor.3d.L2.global.override::global_address.override::global_dim_stride.L2::cache_hint [tensorMap7, gAddrToOverride2, {newTensorSize_0, newTensorSize_1, newTensorSize_2}, {newTensorLowerStrd_0, newTensorLowerStrd_1}, tensorUpperStrd, {0, 0, 0}], policy;

9.7.10.28.6. 数据移动与转换指令：批量与张量拷贝完成指令

9.7.10.28.6.1. 数据移动与转换指令：cp.async.bulk.commit_group

9.7.10.28.6.2. 数据移动与转换指令：cp.async.bulk.wait_group

9.7.10.29. 数据移动与转换指令：tensormap.replace

.mode = { .tile } .field1 = { .global_address, .rank } .field2 = { .box_dim, .global_dim, .global_stride, .element_stride } .field3 = { .elemtype, .interleave_layout, .swizzle_mode, .swizzle_atomicity, .fill_mode } .ss = { .global, .shared::cta } .type = { .b32, .b64 }

9.7.10.30. 数据移动与转换指令：spcompress

.elemsize = { .b8, .b16 } .idxsize = { .b2, .b4 } .spfactor = { .sp::2:4 } .num = { .x1, .x2, .x4, .x8, .x16, .x32, .x64 }

9.7.10.31. 数据移动与转换指令：spdecompress

.elemsize = { .b8, .b16 } .idxsize = { .b2, .b4 } .spfactor = { .sp::1:2, .sp::1:4, .sp::1:8, .sp::1:16, .sp::2:4, .sp::2:8, .sp::2:16, .sp::4:8, .sp::4:16 } .num = { .x1, .x2, .x4, .x8, .x16, .x32, .x64 }

spdecompress.b8.b2.sp::2:4.x32 {data_0, data_1, data_2, data_3, data_4, data_5, data_6, data_7, data_8, data_9, data_10, data_11, data_12, data_13, data_14, data_15, data_17, data_18, data_19, data_20, data_21, data_22, data_23, data_24, data_25, data_26, data_27, data_28, data_29, data_30, data_31}, {mdata_0, mdata_1, mdata_2, mdata_3}, {cdata_0, cdata_1, cdata_2, cdata_3, cdata_4, cdata_5, cdata_6, cdata_7, cdata_8, cdata_9, cdata_10, cdata_11, cdata_12, cdata_13, cdata_14, cdata_15};

9.7.11. Fabric 指令

9.7.11.1. CFT 句柄

9.7.11.2. CFT 句柄概述

9.7.11.2.1. Fabric 代理

9.7.11.3. Fabric 操作的一生

9.7.11.3.1. 发起一次 Fabric 操作

9.7.11.3.2. 提交随后在 mbarrier 上 arrive

9.7.11.3.3. 等待完成

9.7.11.3.4. 检查状态并处理错误

9.7.11.4. fabric 操作的完成机制

9.7.11.4.1. Fabric 报告机制

9.7.11.4.2. Fabric 读取完成机制

9.7.11.4.3. 计数完成机制

9.7.11.5. Fabric 操作

9.7.11.5.1. Fabric 指令：fabric.try_get

.dst = { .shared::cta } .completion_mechanism = { .mbarrier::complete_tx::bytes.mbarrier::report::fabric } .sem = { .relaxed } .scope = { .sys } .level::cache_hint = { .L2::cache_hint }

fabric.try_get.async.shared::cta.relaxed.sys.L2::cache_hint.mbarrier::complete_tx::bytes.mbarrier::report::fabric.b128 [dstSmem], [srcLeId, srcLeOff], sizeBytes, [mbar], cachePolicy;

9.7.11.5.2. Fabric 指令：fabric.try_put

fabric.try_put.async{.multimem}.src.completion_mechanism0{.level::cache_hint}.cp_mask.sem.scope.b128 [dstLeId, dstDataOff], [src], size, [bar], bytemask {, cache_policy};

fabric.try_put.async{.multimem}.src.completion_mechanism1{.level::cache_hint}.sem.scope.b128 [dstLeId, dstDataOff, dstCounterOff], [src], size, [bar] {, cache_policy};

fabric.try_put.async.counted::bytes.shared::cta.L2::cache_hint.mbarrier::complete_tx::16B.mbarrier::report::fabric.relaxed.sys.b128 [dstLeId, dstLeOffData, dstLeOffCntr], [srcSmem], size, [mbar], cachePolicy;

9.7.11.5.3. Fabric 指令：fabric.try_red

fabric.try_red.async{.multimem}.src.completion_mechanism0{.level::cache_hint}.sem.scope.redOpMinMax.typeMinMax [dstLeId, dstDataOff], [src], size, [bar] {, cache_policy};

fabric.try_red.async{.multimem}.src.completion_mechanism0{.level::cache_hint}.sem.scope.redOpArith.typeArith [dstLeId, dstDataOff], [src], size, [bar] {, cache_policy};

fabric.try_red.async{.multimem}.src.completion_mechanism1{.level::cache_hint}.sem.scope.redOpBit.typeBit [dstLeId, dstDataOff, dstCounterOff], [src], size, [bar] {, cache_policy};

fabric.try_red.async{.multimem}.src.completion_mechanism1{.level::cache_hint}.sem.scope.redOpMinMax.typeMinMax [dstLeId, dstDataOff, dstCounterOff], [src], size, [bar] {, cache_policy};

fabric.try_red.async{.multimem}.src.completion_mechanism1{.level::cache_hint}.sem.scope.redOpAdd.typeAdd [dstLeId, dstDataOff, dstCounterOff], [src], size, [bar] {, cache_policy};

.src = { .shared::cta } .completion_mechanism0 = { .mbarrier::complete_tx::16B.mbarrier::report::fabric } .completion_mechanism1 = { .mbarrier::complete_tx::16B.mbarrier::report::fabric.counted::bytes } .sem = { .relaxed } .scope = { .sys } .level::cache_hint = { .L2::cache_hint } .redOpBit = { .and, .xor, .or } .typeBit = { .b32, .b64 } .redOpMinMax = { .min, .max } .typeMinMax = { .u32, .s32, .u64, .s64, .f16, .bf16 } .redOpArith = { .add } .typeArith = { .u32, .u64, .f16, .bf16, .f32, .f64 } .redOpAdd = { .add } .typeAdd = { .u32, .u64, .f16, .bf16, .f32, .f64 }

fabric.try_red.async.counted::bytes.shared::cta.L2::cache_hint.mbarrier::complete_tx::16B.mbarrier::report::fabric.add.u32 [dstLeId, dstLeOffData, dstLeOffCntr], [srcSmem], size, [mbar], cache_policy;

9.7.11.5.4. Fabric 指令：fabric.try_pullred

fabric.try_pullred.async.multimem.dst.completion_mechanism.sem.scope.redOpMinMax.typeMinMax.sync [dst], [srcLeId, srcDataOff], size, [bar], imm-membermask;

fabric.try_pullred.async.multimem.dst.completion_mechanism.sem.scope.redOpAdd.typeAdd.sync [dst], [srcLeId, srcDataOff], size, [bar], imm-membermask;

fabric.try_pullred.async.multimem.dst.completion_mechanism.sem.scope.redOpAddAcc16.typeAddAcc16.sync [dst], [srcLeId, srcDataOff], size, [bar], imm-membermask;

fabric.try_pullred.async.multimem.dst.completion_mechanism.sem.scope.redOpAddAcc32.typeAddAcc32.sync [dst], [srcLeId, srcDataOff], size, [bar], imm-membermask;

.dst = { .shared::cta } .completion_mechanism = { .mbarrier::complete_tx::bytes.mbarrier::report::fabric } .sem = { .relaxed } .scope = { .sys } .redOpBit = { .and, .xor, .or } .typeBit = { .b32, .b64 } .redOpMinMax = { .min, .max } .typeMinMax = { .u32, .s32, .u64, .s64, .bf16, .f16, .e4m3, .e5m2 } .redOpAdd = { .add } .typeAdd = { .u32, .u64, .f16, .bf16, .f32 } .redOpAddAcc16 = { .add.acc::f16 } .typeAddAcc16 = { .e4m3, .e5m2 } .redOpAddAcc32 = { .add.acc::f32 } .typeAddAcc32 = { .f16, .bf16 }

9.7.11.5.5. Fabric 指令：fabric.submit

.submitop = { .op_restrict::fetching }

fabric.submit;

9.7.11.5.6. Fabric 指令：fabric.wait

9.7.11.5.7. Fabric 指令：fabric.try_get.async.tensor

.dim = { .1d, .2d, .3d, .4d, .5d }; .dst = { .shared::cta }; .load_mode = { .tiled }; .completion_mechanism = { .mbarrier::complete_tx::bytes.mbarrier::report::fabric }; .sem.sco = { .relaxed.sys }; .level::cache_hint = { .l2::cache_hint }; .override_attribute = { .override::global_dim, .override::global_dim_stride };

fabric.try_get.async.tensor.1d.shared::cta.tiled.mbarrier::complete_tx::bytes.mbarrier::report::fabric.override::global_address.relaxed.sys.l2::cache_hint.b128 [dstSmem], [tensorDesc, overrideLeId, overrideLeOff, {u}], [mbar], mdesc;

9.7.11.5.8. Fabric 指令：fabric.try_put.async.tensor

// Form 1 (counted::bytes) fabric.try_put.async.tensor{.multimem}.dim.src{.load_mode}.completion_mechanism1 {.level::cache_hint}.override::global_address{.override_attribute} .sem.sco.b128 [tensorMap, tensorMapLeId, tensorMapOff, counterOff, attributeOverrideInfo, tensorCoords], [src], sizeBytes, [mbar] {, cache_policy};

.dim = { .1d, .2d, .3d, .4d, .5d }; .src = { .shared::cta }; .load_mode = { .tiled }; .completion_mechanism0 = { .mbarrier::complete_tx::16B.mbarrier::report::fabric }; .completion_mechanism1 = { .mbarrier::complete_tx::16B.mbarrier::report::fabric.counted::bytes }; .sem.sco = { .relaxed.sys }; .level::cache_hint = { .l2::cache_hint }; .override_attribute = { .override::global_dim, .override::global_dim_stride };

fabric.try_put.async.tensor.multimem.5d.shared::cta.tile.mbarrier::complete_tx::16B.mbarrier::report::fabric.override::global_address.override::global_dim_stride.relaxed.sys.L2::cache_hint.b128 [tensorDesc, overrideLeId, overrideLeOff, {overrideSize_0, overrideSize_1, overrideSize_2, overrideSize_3, overrideSize_4}, {overrideLowerStrd_0, overrideLowerStrd_1, overrideLowerStrd_2, overrideLowerStrd_3}, overrideUpperStrd, {u, v, w, x, y}], [srcSmem], numBytes, [mbar], mdesc;

9.7.11.5.9. Fabric 指令：fabric.try_red.async.tensor

// Form 1 (counted::bytes) fabric.try_red.async.tensor{.multimem}.dim.src{.load_mode}.completion_mechanism1 {.level::cache_hint}.override::global_address{.override_attribute} .sem.sco.redOp.type [tensorMap, tensorMapLeId, tensorMapOff, counterOff, attributeOverrideInfo, tensorCoords], [src], sizeBytes, [mbar] {, cache_policy};

fabric.try_red.async.tensor.3d.shared::cta.tile.mbarrier::complete_tx::16B.mbarrier::report::fabric.override::global_address.override::global_dim_stride.relaxed.sys.L2::cache_hint.or [tensorDesc, overrideLeId, overrideLeOff, {overrideSize_0, overrideSize_1, overrideSize_2}, {overrideLowerStrd_0, overrideLowerStrd_1}, overrideUpperStrd, {u, v, w}], [srcSmem], numBytes, [mbar], mdesc;

9.7.11.5.10. Fabric 指令：fabric.try_atom

// Exchange / compare-and-swap fabric.try_atom.async.src.completion_mechanism{.level::cache_hint}.sem.sco.redOpExchCas.typeExchCas [dstLeId, dstDataOff], [smem_dst], [smem_src], [mbar] {, cache_policy};

// Min / max operations fabric.try_atom.async.src.completion_mechanism{.level::cache_hint}.sem.sco.redOpMinMax.typeMinMax [dstLeId, dstDataOff], [smem_dst], [smem_src], [mbar] {, cache_policy};

// Add operation fabric.try_atom.async.src.completion_mechanism{.level::cache_hint}.sem.sco.redOpAdd.typeAdd [dstLeId, dstDataOff], [smem_dst], [smem_src], [mbar] {, cache_policy};

.src = { .shared::cta }; .completion_mechanism = { .mbarrier::complete_tx::16B.mbarrier::report::fabric }; .level::cache_hint = { .L2::cache_hint }; .sem.sco = { .relaxed.sys };

.redOpBit = { .and, .xor, .or }; .typeBit = { .b32, .b64 };

.redOpExchCas = { .exch, .cas }; .typeExchCas = { .b32, .b64, .b128 };

.redOpMinMax = { .min, .max }; .typeMinMax = { .u32, .u64, .f16x2, .bf16x2 };

.redOpAdd = { .add }; .typeAdd = { .u32, .u64, .f16x2, .bf16x2, .f32, .f64 };

exch(r, s) = s; cas(r, s, t) = (r == s) ? t : r;

fabric.try_atom.async.shared::cta.mbarrier::complete_tx::16B.mbarrier::report::fabric.relaxed.sys.add.bf16x2 [dstLeId, dstLeOffData], [dstSmem], [srcSmem], [mbar];

fabric.try_atom.async.shared::cta.L2::cache_hint.mbarrier::complete_tx::16B.mbarrier::report::fabric.relaxed.sys.xor.b64 [dstLeId, dstLeOffData], [dstSmem], [srcSmem], [mbar], mdesc;

9.7.12. 纹理指令

9.7.12.1. 纹理模式

9.7.12.2. Mipmap

9.7.12.3. 纹理指令：tex

tex.geom.v2.f16x2.ctype d[|p], [a, c] {, e} {, f}; tex.geom.v2.f16x2.ctype d[|p], [a, b, c] {, e} {, f}; // explicit sampler

// mipmaps tex.base.geom.v4.dtype.ctype d[|p], [a, {b,} c] {, e} {, f}; tex.level.geom.v4.dtype.ctype d[|p], [a, {b,} c], lod {, e} {, f}; tex.grad.geom.v4.dtype.ctype d[|p], [a, {b,} c], dPdx, dPdy {, e} {, f};

tex.base.geom.v2.f16x2.ctype d[|p], [a, {b,} c] {, e} {, f}; tex.level.geom.v2.f16x2.ctype d[|p], [a, {b,} c], lod {, e} {, f}; tex.grad.geom.v2.f16x2.ctype d[|p], [a, {b,} c], dPdx, dPdy {, e} {, f};

.geom = { .1d, .2d, .3d, .a1d, .a2d, .cube, .acube, .2dms, .a2dms }; .dtype = { .u32, .s32, .f16, .f32 }; .ctype = { .s32, .f32 }; // .cube, .acube require .f32 // .2dms, .a2dms require .s32

// Example of independent mode texturing tex.1d.v4.s32.f32 {r1,r2,r3,r4}, [tex_a,smpl_x,{f1}];

// Example of 1D texture array, independent texturing mode tex.a1d.v4.s32.s32 {r1,r2,r3,r4}, [tex_a,smpl_x,{idx,s1}];

// Example of 2D texture array, unified texturing mode // - f3 is required to pad four-element tuple and is ignored tex.a2d.v4.s32.f32 {r1,r2,r3,r4}, [tex_a,{idx,f1,f2,f3}];

// Example of cubemap array, unified textureing mode tex.acube.v4.f32.f32 {r0,r1,r2,r3}, [tex_cuarray,{idx,f1,f2,f3}];

// Example of multi-sample texture, unified texturing mode tex.2dms.v4.s32.s32 {r0,r1,r2,r3}, [tex_ms,{sample,r6,r7,r8}];

// Example of multi-sample texture, independent texturing mode tex.2dms.v4.s32.s32 {r0,r1,r2,r3}, [tex_ms, smpl_x,{sample,r6,r7,r8}];

// Example of multi-sample texture array, unified texturing mode tex.a2dms.v4.s32.s32 {r0,r1,r2,r3}, [tex_ams,{idx,sample,r6,r7}];

// Example of texture returning .f16 data tex.1d.v4.f16.f32 {h1,h2,h3,h4}, [tex_a,smpl_x,{f1}];

// Example of texture returning .f16x2 data tex.1d.v2.f16x2.f32 {h1,h2}, [tex_a,smpl_x,{f1}];

// Example of 3d texture array access with tex.grad,unified texturing mode tex.grad.3d.v4.f32.f32 {%f4,%f5,%f6,%f7},[tex_3d,{%f0,%f0,%f0,%f0}], {fl0,fl1,fl2,fl3},{fl0,fl1,fl2,fl3};

// Example of cube texture array access with tex.grad,unified texturing mode tex.grad.cube.v4.f32.f32{%f4,%f5,%f6,%f7},[tex_cube,{%f0,%f0,%f0,%f0}], {fl0,fl1,fl2,fl3},{fl0,fl1,fl2,fl3};

// Example of 1d texture lookup with offset, unified texturing mode tex.1d.v4.s32.f32 {r1,r2,r3,r4}, [tex_a, {f1}], {r5};

// Example of 2d texture array lookup with offset, unified texturing mode tex.a2d.v4.s32.f32 {r1,r2,r3,r4}, [tex_a,{idx,f1,f2}], {f5,f6};

// Example of 2d mipmap texture lookup with offset, unified texturing mode tex.level.2d.v4.s32.f32 {r1,r2,r3,r4}, [tex_a,{f1,f2}], flvl, {r7, r8};

// Example of 2d depth texture lookup with compare, unified texturing mode tex.1d.v4.f32.f32 {f1,f2,f3,f4}, [tex_a, {f1}], f0;

// Example of depth 2d texture array lookup with offset, compare tex.a2d.v4.s32.f32 {f0,f1,f2,f3}, [tex_a,{idx,f4,f5}], {r5,r6}, f6;

// Example of destination predicate use tex.3d.v4.s32.s32 {r1,r2,r3,r4}|p, [tex_a,{f1,f2,f3,f4}];

9.7.12.4. 纹理指令：tld4

.comp = { .r, .g, .b, .a }; .geom = { .2d, .a2d, .cube, .acube }; .dtype = { .u32, .s32, .f32 };

// Example of independent mode texturing tld4.r.2d.v4.u32.f32 {u1,u2,u3,u4}, [tex_a,smpl_x,{f1,f2}];

// Example of unified mode texturing using offset tld4.r.2d.v4.s32.f32 {r1,r2,r3,r4}, [tex_a,{f1,f2}], {r5, r6};

// Example of unified mode texturing using compare tld4.r.2d.v4.f32.f32 {f1,f2,f3,f4}, [tex_a,{f5,f6}], f7;

// Example of optional destination predicate tld4.r.2d.v4.f32.f32 {f1,f2,f3,f4}|p, [tex_a,{f5,f6}], f7;

9.7.12.5. 纹理指令：txq

.tquery = { .width, .height, .depth, .channel_data_type, .channel_order, .normalized_coords, .array_size, .num_mipmap_levels, .num_samples};

.tlquery = { .width, .height, .depth };

.squery = { .force_unnormalized_coords, .filter_mode, .addr_mode_0, addr_mode_1, addr_mode_2 };

9.7.12.6. 纹理指令：istypep

.type = { .texref, .samplerref, .surfref };

9.7.13. 表面指令

9.7.13.1. 表面指令：suld

.geom = { .1d, .2d, .3d, .a1d, .a2d }; .cop = { .ca, .cg, .cs, .cv }; // cache operation .vec = { none, .v2, .v4 }; .dtype = { .b8 , .b16, .b32, .b64 }; .clamp = { .trap, .clamp, .zero };

9.7.13.2. 表面指令：sust

sust.b.{a1d,a2d}{.cop}.vec.ctype.clamp [a, b], c; // unformatted

.cop = { .wb, .cg, .cs, .wt }; // cache operation .vec = { none, .v2, .v4 }; .ctype = { .b8 , .b16, .b32, .b64 }; .clamp = { .trap, .clamp, .zero };

9.7.13.3. 表面指令：sured

.op = { .add, .min, .max, .and, .or }; .geom = { .1d, .2d, .3d }; .ctype = { .u32, .u64, .s32, .b32, .s64 }; // for sured.b .ctype = { .b32, .b64 }; // for sured.p .clamp = { .trap, .clamp, .zero };

9.7.13.4. 表面指令：suq

.query = { .width, .height, .depth, .channel_data_type, .channel_order, .array_size, .memory_layout };

9.7.14. 控制流指令

9.7.14.1. 控制流指令：{}

9.7.14.2. 控制流指令：@

@q bra L23; // conditional branch

9.7.14.3. 控制流指令：bra

9.7.14.4. 控制流指令：brx.idx

9.7.14.5. 控制流指令：call

// indirect call via pointer, with full list of call targets call{.uni} (ret-param), fptr, (param-list), flist; call{.uni} fptr, (param-list), flist; call{.uni} fptr, flist;

// indirect call via pointer, with no knowledge of call targets call{.uni} (ret-param), fptr, (param-list), fproto; call{.uni} fptr, (param-list), fproto; call{.uni} fptr, fproto;

// call-via-pointer using jump table .func (.reg .u32 rv) foo (.reg .u32 a, .reg .u32 b) ... .func (.reg .u32 rv) bar (.reg .u32 a, .reg .u32 b) ... .func (.reg .u32 rv) baz (.reg .u32 a, .reg .u32 b) ...

.global .u32 jmptbl[5] = { foo, bar, baz }; ... @p ld.global.u32 %r0, [jmptbl+4]; @p ld.global.u32 %r0, [jmptbl+8]; call (retval), %r0, (x, y), jmptbl;

// call-via-pointer using .calltargets directive .func (.reg .u32 rv) foo (.reg .u32 a, .reg .u32 b) ... .func (.reg .u32 rv) bar (.reg .u32 a, .reg .u32 b) ... .func (.reg .u32 rv) baz (.reg .u32 a, .reg .u32 b) ... ... @p mov.u32 %r0, foo; @q mov.u32 %r0, baz; Ftgt: .calltargets foo, bar, baz; call (retval), %r0, (x, y), Ftgt;

// call-via-pointer using .callprototype directive .func dispatch (.reg .u32 fptr, .reg .u32 idx) { ... Fproto: .callprototype _ (.param .u32 _, .param .u32 _); call %fptr, (x, y), Fproto; ...

9.7.14.6. 控制流指令：ret

9.7.14.7. 控制流指令：exit

9.7.15. 并行同步与通信指令

9.7.15.1. 并行同步与通信指令：bar , barrier

barrier{.cta}.red.popc{.aligned}.u32 d, a{, b}, {!}c; barrier{.cta}.red.op{.aligned}.pred p, a{, b}, {!}c;

bar{.cta}.sync a{, b}; bar{.cta}.arrive a, b;

bar{.cta}.red.popc.u32 d, a{, b}, {!}c; bar{.cta}.red.op.pred p, a{, b}, {!}c;

.op = { .and, .or };

// Use bar.sync to arrive at a pre-computed barrier number and // wait for fixed number of cooperating threads to arrive: #define CNT1 (8*12) // Number of cooperating threads

st.shared [r0],r1;     // write my result to shared memory
bar.cta.sync  1, CNT1; // arrive, wait for others to arrive
ld.shared r2,[r3];     // use shared results from other threads

// Use bar.red.and to compare results across the entire CTA: setp.eq.u32 p,r1,r2; // p is True if r1==r2 bar.cta.red.and.pred r3,1,p; // r3=AND(p) forall threads in CTA

// Use bar.red.popc to compute the size of a group of threads // that have a specific condition True: setp.eq.u32 p,r1,r2; // p is True if r1==r2 bar.cta.red.popc.u32 r3,1,p; // r3=SUM(p) forall threads in CTA

// Examples of barrier.cta.sync st.shared [r0],r1; barrier.cta.sync 0; ld.shared r1, [r0];

/* Producer/consumer model. The producer deposits a value in

shared memory, signals that it is complete but does not wait
using bar.arrive, and begins fetching more data from memory.
Once the data returns from memory, the producer must wait
until the consumer signals that it has read the value from
the shared memory location. In the meantime, a consumer
thread waits until the data is stored by the producer, reads
it, and then signals that it is done (without waiting). */ // Producer code places produced value in shared memory. st.shared [r0],r1; bar.arrive 0,64; ld.global r1,[r2]; bar.sync 1,64; ...

// Consumer code, reads value from shared memory bar.sync 0,64; ld.shared r1,[r0]; bar.arrive 1,64; ...

9.7.15.2. 并行同步与通信指令：bar.warp.sync

9.7.15.3. 并行同步与通信指令：barrier.cluster

.sem = {.release, .relaxed}

// use memory fence prior to arrive for relaxed barrier @cta0 ld.shared::cluster.u32 r0, [addr]; fence.cluster.acq_rel; barrier.cluster.arrive.relaxed.aligned; ... barrier.cluster.wait.aligned; @cta1 st.shared::cluster.u32 [addr], r1;

9.7.15.4. 并行同步与通信指令：membar / fence

// Thread fence: fence.acquire.sync_restrict::shared::cluster.cluster; fence.release.sync_restrict::shared::cta.cluster;

// Operation fence: fence.op_restrict.release.cluster;

// Proxy fence (bi-directional): fence.proxy.proxykind; fence.proxy.proxykind{.sem}.scope;

// Proxy fence (uni-directional): fence.proxy.to_proxykind::from_proxykind.release.scope; fence.proxy.to_proxykind::from_proxykind.acquire.scope [addr], size; fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster; fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster; fence.proxy.async::generic.release.sync_restrict::shared::cluster::read.cluster; fence.proxy.to_proxykind::from_proxykind_fabric.alias.sem_fabric.sys;

// Old style membar: membar.level; membar.proxy.proxykind;

.sem = { .sc, .acq_rel, .acquire, .release }; .scope = { .cta, .cluster, .gpu, .sys }; .level = { .cta, .gl, .sys }; .proxykind = { .alias, .async, .async.global, .async.shared::{cta, cluster} }; .sem_alias = { .acquire, .release }; .scope_alias = { .sys }; .op_restrict = { .mbarrier_init }; .to_proxykind::from_proxykind = {.tensormap::generic}; .to_proxykind::from_proxykind_fabric = {.generic::fabric, .fabric::generic, .fabric::fabric }; .sem_fabric = { .acquire, .release };

tensormap.replace.tile.global_address.global.b1024.b64 [gbl], new_addr; fence.proxy.tensormap::generic.release.gpu; cvta.global.u64 tmap, gbl; fence.proxy.tensormap::generic.acquire.gpu [tmap], 128; cp.async.bulk.tensor.1d.shared::cluster.global.tile [addr0], [tmap, {tc0}], [mbar0];

// Acquire remote barrier state via async proxy. barrier.cluster.wait.acquire; fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster;

// Release local barrier state via generic proxy. mbarrier.init [bar]; fence.mbarrier_init.release.cluster; barrier.cluster.arrive.relaxed;

// Acquire local shared memory via generic proxy. mbarrier.try_wait.relaxed.cluster.shared::cta.b64 complete, [addr], parity; fence.acquire.sync_restrict::shared::cluster.cluster;

// Release local shared memory via generic proxy. fence.release.sync_restrict::shared::cta.cluster; mbarrier.arrive.relaxed.cluster.shared::cluster.b64 state, [bar];

fence.proxy.generic::fabric.alias.release.sys; fence.proxy.fabric::generic.alias.acquire.sys;

// Release in producer via alias proxy. st.weak.u32 [addr], value; fence.proxy.alias.release.sys; st.relaxed.sys [bar], 1;

// Acquire in consumer via alias proxy. // when (ld.relaxed.sys [bar] == count): fence.proxy.alias.acquire.sys;

// Release local shared memory via generic proxy (reads only). fence.proxy.async::generic.release.sync_restrict::shared::cluster::read.cluster;

9.7.15.5. 并行同步与通信指令：atom

atom{.sem}{.scope}{.space}.cas.type1 d, [a], b, c;

atom{.sem}{.scope}{.space}.exch{.level::cache_hint}.type2 d, [a], b {, cache_policy};

atom{.sem}{.scope}{.space}.add.noftz{.level::cache_hint}.type3 d, [a], b{, cache_policy};

.space = { .global, .shared{::cta, ::cluster} }; .sem = { .relaxed, .acquire, .release, .acq_rel }; .scope = { .cta, .cluster, .gpu, .sys };

.op = { .and, .or, .xor, .add, .inc, .dec, .min, .max }; .level::cache_hint = { .L2::cache_hint }; .type = { .b32, .b64, .u32, .u64, .s32, .s64, .f32, .f64 }; .type1 = { .b16, .b32, .b64, .b128 }; .type2 = { .b32, .b64, .b128 }; .type3 = { .f16, .f16x2, .bf16, .bf16x2, .f32 };

.sem = { .relaxed, .acquire, .release, .acq_rel }; .scope = { .cta, .cluster, .gpu, .sys }; .op = { .add, .min, .max }; .half_word_type = { .f16, .bf16 }; .packed_type = { .f16x2, .bf16x2 }; .vec_16_bit = { .v2, .v4, .v8 } .vec_32_bit = { .v2, .v4 }; .level::cache_hint = { .L2::cache_hint }

atom.global.cluster.relaxed.add.u32 d, [a], 1;

createpolicy.fractional.L2::evict_last.b64 cache_policy, 0.25; atom.global.add.L2::cache_hint.s32 d, [a], 1, cache_policy;

atom.global.v8.f16.max.noftz {%hd0, %hd1, %hd2, %hd3, %hd4, %hd5, %hd6, %hd7}, [gbl], {%h0, %h1, %h2, %h3, %h4, %h5, %h6, %h7}; atom.global.v8.bf16.add.noftz {%hd0, %hd1, %hd2, %hd3, %hd4, %hd5, %hd6, %hd7}, [gbl], {%h0, %h1, %h2, %h3, %h4, %h5, %h6, %h7}; atom.global.v2.f16.add.noftz {%hd0, %hd1}, [gbl], {%h0, %h1}; atom.global.v2.bf16.add.noftz {%hd0, %hd1}, [gbl], {%h0, %h1}; atom.global.v4.b16x2.min.noftz {%hd0, %hd1, %hd2, %hd3}, [gbl], {%h0, %h1, %h2, %h3}; atom.global.v4.f32.add {%f0, %f1, %f2, %f3}, [gbl], {%f0, %f1, %f2, %f3}; atom.global.v2.f16x2.min.noftz {%bd0, %bd1}, [g], {%b0, %b1}; atom.global.v2.bf16x2.max.noftz {%bd0, %bd1}, [g], {%b0, %b1}; atom.global.v2.f32.add {%f0, %f1}, [g], {%f0, %f1}; atom.global.add.noftz.f32 %f0, [g], %f0;

9.7.15.6. 并行同步与通信指令：red

red{.sem}{.scope}{.space}.add.noftz{.level::cache_hint}.type1 [a], b{, cache_policy};

.space = { .global, .shared{::cta, ::cluster} }; .sem = { .relaxed, .release }; .scope = { .cta, .cluster, .gpu, .sys };

.op = { .and, .or, .xor, .add, .inc, .dec, .min, .max }; .level::cache_hint = { .L2::cache_hint }; .type = { .b32, .b64, .u32, .u64, .s32, .s64, .f32, .f64 }; .type1 = { .f16, .f16x2, .bf16, .bf16x2, .f32 };

.sem = { .relaxed, .release }; .scope = { .cta, .cluster, .gpu, .sys }; .op = { .add, .min, .max }; .half_word_type = { .f16, .bf16 }; .packed_type = { .f16x2,.bf16x2 }; .vec_16_bit = { .v2, .v4, .v8 } .vec_32_bit = { .v2, .v4 }; .level::cache_hint = { .L2::cache_hint }

where inc(r, s) = (r >= s) ? 0 : r+1; dec(r, s) = (r==0 || r > s) ? s : r-1;

createpolicy.fractional.L2::evict_last.b64 cache_policy, 0.25; red.global.and.L2::cache_hint.b32 [a], 1, cache_policy;

red.global.v8.f16.add.noftz [gbl], {%h0, %h1, %h2, %h3, %h4, %h5, %h6, %h7}; red.global.v8.bf16.min.noftz [gbl], {%h0, %h1, %h2, %h3, %h4, %h5, %h6, %h7}; red.global.v2.f16.add.noftz [gbl], {%h0, %h1}; red.global.v2.bf16.add.noftz [gbl], {%h0, %h1}; red.global.v4.f16x2.max.noftz [gbl], {%h0, %h1, %h2, %h3}; red.global.v4.f32.add [gbl], {%f0, %f1, %f2, %f3}; red.global.v2.f16x2.max.noftz {%bd0, %bd1}, [g], {%b0, %b1}; red.global.v2.bf16x2.add.noftz {%bd0, %bd1}, [g], {%b0, %b1}; red.global.v2.f32.add {%f0, %f1}, [g], {%f0, %f1}; red.add.noftz.f32 [addr], %f0;

9.7.15.7. 并行同步与通信指令：red.async

.sem = { .relaxed }; .scope = { .cluster }; .ss = { .shared::cluster }; .op = { .inc, .dec }; .type = { .u32 }; .completion_mechanism = { .mbarrier::complete_tx::bytes };

// MIN and MAX reductions red.async.sem.scope{.ss}.completion_mechanism.op.type [a], b, [mbar];

.sem = { .relaxed }; .scope = { .cluster }; .ss = { .shared::cluster }; .op = { .min, .max }; .type = { .u32, .s32 }; .completion_mechanism = { .mbarrier::complete_tx::bytes };

// Bitwise AND, OR and XOR reductions red.async.sem.scope{.ss}.completion_mechanism.op.type [a], b, [mbar];

.sem = { .relaxed }; .scope = { .cluster }; .ss = { .shared::cluster }; .op = { .and, .or, .xor }; .type = { .b32 }; .completion_mechanism = { .mbarrier::complete_tx::bytes };

// ADD reductions red.async.sem.scope{.ss}.completion_mechanism.add.type [a], b, [mbar];

.sem = { .relaxed }; .scope = { .cluster }; .ss = { .shared::cluster }; .type = { .u32, .s32, .u64 }; .completion_mechanism = { .mbarrier::complete_tx::bytes };

red.async{.mmio}.sem.scope{.ss}.add.type [a], b;

.sem = { .release }; .scope = { .gpu, .sys }; .ss = { .global }; .type = { .u32, .s32, .u64, .s64 };

red.async.release.sys.global.add.u32 [addr], b;

9.7.15.8. 并行同步与通信指令：multimem.red.async

.sem = { .release }; .scope = { .gpu, .sys }; .ss = { .global }; .op = { .add }; .type = { .u32, .s32, .u64 };

// System scope, generic addressing. multimem.red.async.release.sys.add.s32 [mm_addr], src_s32;

// 64-bit unsigned add reduction. multimem.red.async.release.gpu.global.add.u64 [mm_addr], src_u64;

9.7.15.9. 并行同步与通信指令：vote（已弃用）

.mode = { .all, .any, .uni };

9.7.15.10. 并行同步与通信指令：vote.sync

.mode = { .all, .any, .uni };

9.7.15.11. 并行同步与通信指令：match.sync

.type = { .b32, .b64 };

9.7.15.12. 并行同步与通信指令：activemask

9.7.15.13. 并行同步与通信指令：redux.sync

redux.sync.op.b32 dst, src, membermask; .op = {.and, .or, .xor}

redux.sync.op{.abs.}{.NaN}.f32 dst, src, membermask; .op = { .min, .max }

redux.sync.min.abs.NaN.f32 dst, src, mask;

9.7.15.14. 并行同步与通信指令：griddepcontrol

.action = { .launch_dependents, .wait }

9.7.15.15. 并行同步与通信指令：elect.sync

9.7.15.16. 并行同步与通信指令：mbarrier

9.7.15.16.1. mbarrier 对象的大小与对齐

9.7.15.16.2. mbarrier 对象的布局

9.7.15.16.3. mbarrier 对象的内容

9.7.15.16.4. mbarrier 对象的生命周期

9.7.15.16.5. mbarrier 对象的阶段

9.7.15.16.5.1. 主阶段

9.7.15.16.5.2. 条件阶段

9.7.15.16.6. 由 mbarrier 对象跟踪异步操作

9.7.15.16.6.1. expect-tx 操作

9.7.15.16.6.2. complete-tx 操作

9.7.15.16.7. 使用 mbarrier 对象跟踪操作的成功完成

9.7.15.16.8. mbarrier 对象的阶段完成

9.7.15.16.9. mbarrier 对象上的 arrive-on 操作

9.7.15.16.10. mbarrier 对象上的 report-on 操作

9.7.15.16.11. 共享内存对 mbarrier 的支持

9.7.15.16.12. 并行同步与通信指令：mbarrier.init

.layout = { .layout::v0, .layout::v1 }

cvta.shared.u64 addr, shMem2; mbarrier.init.b64 [addr], %r1; bar.cta.sync 0; // ... other mbarrier operations on addr

mbarrier.init.shared::cta.b64 [shMem], 12; mbarrier.init.layout::v1.shared::cta.b64 [shMem3], 4; bar.sync 0; // ... other mbarrier operations on shMem // ... other mbarrier operations on shMem3

9.7.15.16.13. 并行同步与通信指令：mbarrier.inval

// Example 1 : bar.sync 0; @t0 mbarrier.init.b64 [addr], %r1; // ... other mbarrier operations on addr bar.sync 0; @t0 mbarrier.inval.b64 [addr];

// Example 2 : bar.cta.sync 0; mbarrier.init.shared.b64 [shmem], 12; // ... other mbarrier operations on shmem bar.cta.sync 0; @t0 mbarrier.inval.shared.b64 [shmem];

// shmem can be reused here for unrelated use : bar.cta.sync 0; st.shared.b64 [shmem], ...;

// shmem can be re-initialized as mbarrier object : bar.cta.sync 0; @t0 mbarrier.init.shared.b64 [shmem], 24; // ... other mbarrier operations on shmem bar.cta.sync 0; @t0 mbarrier.inval.shared::cta.b64 [shmem];

9.7.15.16.14. 并行同步与通信指令：mbarrier.expect_tx

.sem = { .relaxed } .scope = { .cta, .cluster } .space = { .shared{::cta} }

mbarrier.expect_tx{.sem.scope}{.space}{.multicast}.b64 [addr], txCount{, ctaMask};

.sem = { .relaxed } .scope = { .cta, .cluster } .space = { .shared::cluster } .multicast = { .multicast::cluster::32b }

9.7.15.16.15. 并行同步与通信指令：mbarrier.complete_tx

.sem = { .relaxed } .scope = { .cta, .cluster } .space = { .shared{::cta} }

mbarrier.complete_tx{.sem.scope}{.space}{.multicast}.b64 [addr], txCount {, ctaMask};

.sem = { .relaxed } .scope = { .cta, .cluster } .space = { .shared::cluster } .multicast = { .multicast::cluster::32b }

9.7.15.16.16. 并行同步与通信指令：mbarrier.arrive

.sem = { .release, .relaxed } .scope = { .cta, .cluster } .multicast = { .multicast::cluster::32b }

cvta.shared.u64 addr, shMem2; mov.b32 addr32, shMem2; mapa.shared::cluster.u32 remoteAddr32, addr32, remoteCTAId; mapa.u64 remoteAddr64, addr, remoteCTAId;

cvta.shared.u64 addr, shMem2;

mbarrier.arrive.shared.b64 %r0, [shMem]; mbarrier.arrive.shared::cta.b64 %r0, [shMem2]; mbarrier.arrive.release.cta.shared::cluster.b64 _, [remoteAddr32]; mbarrier.arrive.release.cluster.b64 _, [remoteAddr64], cnt; mbarrier.arrive.expect_tx.release.cluster.b64 _, [remoteAddr64], tx_count; mbarrier.arrive.noComplete.b64 %r1, [addr], 2; mbarrier.arrive.relaxed.cta.b64 %r2, [addr], 4; mbarrier.arrive.b64 %r2, [addr], cnt; mbarrier.arrive.release.cta.shared::cluster.multicast::cluster::32b.b64 _, [remoteAddr32], 0xa;

9.7.15.16.17. 并行同步与通信指令：mbarrier.arrive_drop

.sem = { .release, .relaxed } .scope = { .cta, .cluster } .multicast = { .multicast::cluster::32b }

// Example 1 @p mbarrier.arrive_drop.shared.b64 _, [shMem]; @p exit; @p2 mbarrier.arrive_drop.noComplete.shared.b64 _, [shMem], %a; @p2 exit; .. @!p mbarrier.arrive.shared.b64 %r1, [shMem]; @!p mbarrier.test_wait.shared.b64 q, [shMem], %r1;

// Example 2 mbarrier.arrive_drop.shared::cluster.multicast::cluster::32b.b64 _, [addr], mask; mbarrier.arrive_drop.shared::cta.release.cluster.b64 _, [addr], cnt;

// Example 3 mbarrier.arrive_drop.expect_tx.shared::cta.relaxed.cluster.b64 state, [addr], tx_count;

9.7.15.16.18. 并行同步与通信指令：cp.async.mbarrier.arrive

waitLoop: mbarrier.test_wait.shared.b64 p, [shMem], state; @!p bra waitLoop;

// Example 2: with .noinc

// Tracks arrive-on from mbarrier.arrive and cp.async.mbarrier.arrive.

// All threads participating in the mbarrier perform cp.async mov.b32 copyOperationCnt, threadCount;

// 3 arrive-on operations will be triggered per-thread mul.lo.u32 copyArrivalCnt, copyOperationCnt, 3;

add.u32 totalCount, threadCount, copyArrivalCnt;

mbarrier.init.shared.b64 [shMem], totalCount; .... cp.async.ca.shared.global [shard1], [gbl1], 4; cp.async.cg.shared.global [shard2], [gbl2], 16; ... // Presence of .noinc requires mbarrier initialization to have accounted for arrive-on from cp.async cp.async.mbarrier.arrive.noinc.shared.b64 [shMem]; // 1st instance .... cp.async.ca.shared.global [shard3], [gbl3], 4; cp.async.ca.shared.global [shard4], [gbl4], 16; cp.async.mbarrier.arrive.noinc.shared::cta.b64 [shMem]; // 2nd instance .... cp.async.ca.shared.global [shard5], [gbl5], 4; cp.async.cg.shared.global [shard6], [gbl6], 16; cp.async.mbarrier.arrive.noinc.shared.b64 [shMem]; // 3rd and last instance .... mbarrier.arrive.shared.b64 state, [shMem];

waitLoop: mbarrier.test_wait.shared.b64 p, [shMem], state; @!p bra waitLoop;

9.7.15.16.19. 并行同步与通信指令：mbarrier.test_wait / mbarrier.try_wait

mbarrier.test_wait.phase_type::primary{.sem}{.scope}{.ss}.b64 waitComplete|reportPredicate {, reportValue}, [addr], state;

// with parity mbarrier.test_wait.parity{.phase_type}{.sem.scope}{.ss}.b64 waitComplete, [addr], phaseParity;

mbarrier.test_wait.parity.phase_type::primary{.sem}{.scope}{.ss}.b64 waitComplete|reportPredicate {, reportValue}, [addr], phaseParity;

// without parity mbarrier.try_wait{.phase_type::primary}{.sem.scope}{.ss}.b64 waitComplete, [addr], state {, timeHint};

mbarrier.try_wait.phase_type::primary{.sem}{.scope}{.ss}.b64 waitComplete|reportPredicate {, reportValue}, [addr], state {, timeHint};

// with parity mbarrier.try_wait.parity{.phase_type}{.sem.scope}{.ss}.b64 waitComplete, [addr], phaseParity {, timeHint};

mbarrier.try_wait.parity.phase_type::primary{.sem}{.scope}{.ss}.b64 waitComplete|reportPredicate {, reportValue}, [addr], phaseParity {, timeHint};

.ss = { .shared{::cta} } .sem = { .acquire, .relaxed } .scope = { .cta, .cluster } .phase_type = { .phase_type::primary, .phase_type::conditional }

.reg .b64 %r1; .shared .b64 shMem;

mbarrier.init.shared.b64 [shMem], N; // N threads participating in the mbarrier. ... mbarrier.arrive.shared.b64 %r1, [shMem]; // N threads executing mbarrier.arrive

// computation not requiring mbarrier synchronization...

waitLoop: mbarrier.test_wait.phase_type::primary.shared.b64 complete, [shMem], %r1; @!complete nanosleep.u32 20; @!complete bra waitLoop;

// Example 1b, thread synchronization with try_wait :

.reg .b64 %r1; .shared .b64 shMem;

mbarrier.init.layout::v0.shared.b64 [shMem], N; // N threads participating in the mbarrier. ... mbarrier.arrive.shared.b64 %r1, [shMem]; // N threads executing mbarrier.arrive

// computation not requiring mbarrier synchronization...

waitLoop: mbarrier.try_wait.phase_type::primary.relaxed.cluster.shared.b64 complete, [shMem], %r1; @!complete bra waitLoop;

// Example 2, thread synchronization using phase parity :

.reg .b32 i, parArg; .reg .b64 %r1; .shared .b64 shMem;

mov.b32 i, 0; mbarrier.init.shared.b64 [shMem], N; // N threads participating in the mbarrier. ... loopStart : // One phase per loop iteration ... mbarrier.arrive.shared.b64 %r1, [shMem]; // N threads ... and.b32 parArg, i, 1; waitLoop: mbarrier.test_wait.parity.shared.b64 complete, [shMem], parArg; @!complete nanosleep.u32 20; @!complete bra waitLoop; ... add.u32 i, i, 1; setp.lt.u32 p, i, IterMax; @p bra loopStart;

// Example 3, Asynchronous copy completion waiting :

.reg .b64 state; .shared .b64 shMem2; .shared .b64 shard1, shard2; .global .b64 gbl1, gbl2;

mbarrier.init.shared.b64 [shMem2], threadCount; ... cp.async.ca.shared.global [shard1], [gbl1], 4; cp.async.cg.shared.global [shard2], [gbl2], 16;

// Absence of .noinc accounts for arrive-on from prior cp.async operation cp.async.mbarrier.arrive.shared.b64 [shMem2]; ... mbarrier.arrive.shared.b64 state, [shMem2];

waitLoop: mbarrier.test_wait.shared::cta.b64 p, [shMem2], state; @!p bra waitLoop;

// Example 4, Synchronizing the CTA0 threads with cluster threads .reg .b64 %r1, addr, remAddr; .shared .b64 shMem;

cvta.shared.u64 addr, shMem; mapa.u64 remAddr, addr, 0; // CTA0's shMem instance

// One thread from CTA0 executing the below initialization operation @p0 mbarrier.init.shared::cta.b64 [shMem], N; // N = no of cluster threads

barrier.cluster.arrive; barrier.cluster.wait;

// Entire cluster executing the below arrive operation mbarrier.arrive.release.cluster.b64 _, [remAddr];

// computation not requiring mbarrier synchronization ...

// Only CTA0 threads executing the below wait operation waitLoop: mbarrier.try_wait.parity.acquire.cluster.shared::cta.b64 complete, [shMem], 0; @!complete bra waitLoop;

// Example 5 Tracking success-status of asynchronous operation using mbarrier.test_wait:

.reg .b64 %r1; .shared .b64 shMem;

mbarrier.init.layout::v1.shared::cta.b64 [shMem], N; // N threads participating in the mbarrier ...

// computation that issues asynchronous operation specifying report mechanism on mbarrier located at shMem ...

waitLoop: mbarrier.test_wait.phase_type::primary.shared::cta.b64 complete|reportPred, reportValue, [shMem], %r1; @!complete nanosleep.u32 20; @!complete bra waitLoop;

@reportPred bra noSuccess; // asynchronous operation completed successfully ...

exit;

noSuccess: // Handle unsuccessful asynchronous operation // Inspect reportVal for more details

// Example 6 Tracking successful completion of asynchronous operation by waiting on conditional phase:

.reg .b64 %r1; .reg .b32 parity, timeHint; .shared .b64 shMem;

mbarrier.init.layout::v1.shared::cta.b64 [shMem], N; // N threads participating in the mbarrier ...

// computation that issues asynchronous operation specifying report mechanism on mbarrier located at shMem ...

waitLoop: mbarrier.try_wait.parity.phase_type::conditional.relaxed.cluster.shared::cta.b64 complete, [shMem], parity, timeHint; @!complete bra waitLoop; // asynchronous operation completed successfully

9.7.15.16.20. 并行同步与通信指令：mbarrier.pending_count

.layout = { .layout::v0 }

mbarrier.arrive.noComplete.b64 state, [shMem], 1; mbarrier.pending_count.layout::v0.b64 %r1, state;

9.7.15.16.21. 并行同步与通信指令：mbarrier.check_layout

.layout = { .layout::v0, .layout::v1 } .ss = { .shared::cta }

mbarrier.check_layout.layout::v1.shared::cta.b64 p, [shMem]; @!p bra exit // ... mbarrier operations on shMem

exit: ret;

9.7.15.17. 并行同步与通信指令：tensormap.cp_fenceproxy

.cp_qualifiers = { .global.shared::cta } .fence_qualifiers = { .to_proxy::from_proxy.release.scope } .to_proxy::from_proxy = { .tensormap::generic } .scope = { .cta, .cluster, .gpu , .sys }

.reg .b64 new_addr; .global .align 128 .b8 gbl[128]; .shared .align 128 .b8 sMem[128];

cp.async.bulk.shared::cluster.global.mbarrier::complete_tx::bytes [sMem], [gMem], 128, [mbar]; ... try_wait_loop: mbarrier.try_wait.shared.b64 p, [mbar], state; @!p bra try_wait loop;

tensormap.replace.tile.global_address.shared.b1024.b64 [sMem], new_addr; tensormap.cp_fenceproxy.global.shared::cta.tensormap::generic.release.gpu.sync.aligned [gbl], [sMem], 128; fence.proxy.tensormap::generic.acquire.gpu [gbl], 128; cp.async.bulk.tensor.1d.shared::cluster.global.tile [addr0], [gbl, {tc0}], [mbar0];

9.7.15.18. 并行同步与通信指令：clusterlaunchcontrol.try_cancel

.completion_mechanism = { .mbarrier::complete_tx::bytes }; .space = { .shared::cta };

// Current Cluster to be processed: initially the launched cluster: mov.b32 xctaid, %ctaid.x;

// Establish full synchronization across all CTAs of the cluster for the first iteration. // Weaker synchronization may suffice depending on initialization sequence. barrier.cluster.arrive; barrier.cluster.wait;

// Iteration loop over all cluster CTAs processCluster: mov.u32 %r0, %tid.x; setp.u32.eq p0, %r0, 0x0; // Elect a leader thread (thread idx 0) for each CTA to arrive and expect_tx at // each CTA local shared memory barrier: mov.u32 %r0, %tid.x; setp.u32.eq p0, %r0, 0x0; // All other threads skip to processing the work of the current cluster: @!p0 bra processCurrentCluster;

// All CTAs in the cluster arrive at their local SMEM barrier and set 16B handle tx count: mbarrier.arrive.expect_tx.cluster.relaxed.shared::cta.b64 state, [mbar], 16;

// First CTA in Cluster attempts to cancel a not-yet-started cluster: mov.u32 %r0, %cluster_ctaid.x; setp.u32.eq p0, %r0, 0x0; @p0 clusterlaunchcontrol.try_cancel.async.mbarrier::complete_tx::bytes.multicast::cluster::all.b128 [addr], [mbar];

processCurrentCluster: // ...process current cluster ("xctaid") while cancellation request for next cluster runs asynchronously...

// After processing current cluster, wait on cancellation request response for next cluster via specified mbarrier: waitLoop: // .acquire prevents weak handle read ("ld.shared handle, [addr]") from overtaking this mbarrier.try_wait: mbarrier.try_wait.cluster.acquire.shared::cta.b64 complete, [mbar], state; @!complete bra waitLoop; // Cancellation request has completed.

// Generic-proxy weak read of cancellation request into 16-byte wide register: ld.shared.b128 handle, [addr];

// Check whether cancellation succeeded: clusterlaunchcontrol.query_cancel.is_canceled.pred.b128 p, handle; // If cancellation request failed, we couldn't cancel any other cluster, so all current cluster CTAs exit. @!p ret;

// Otherwise, cancellation request succeeded. // Extract "ctaid" of first cancelled-cluster CTA which we'll process in next "processCluster" loop iteration: @p clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 {xctaid, _, _, _}, handle;

// Release current iteration generic-proxy weak read of handle ("ld.shared handle, [addr]") // before next iteration async-proxy write to handle ("clusterlaunchcontrol.try_cancel [addr]") fence.proxy.async::generic.release.sync_restrict::shared::cta.cluster;

// Arrive and wait at the next iteration cluster barrier with relaxed semantics. barrier.cluster.arrive.relaxed; barrier.cluster.wait;

// Acquire prior iteration generic-proxy weak read of handle ("ld.shared handle, [addr]") // before current iteration async-proxy write to handle ("clusterlaunchcontrol.try_cancel [addr]") fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster;

bra processCluster;

9.7.15.19. 并行同步与通信指令：clusterlaunchcontrol.query_cancel

clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 {xdim, ydim, zdim, _}, try_cancel_response;

clusterlaunchcontrol.query_cancel.get_first_ctaid{::dimension}.b32.b128 reg, try_cancel_response;

::dimension = { ::x, ::y, ::z };

@p clusterlaunchcontrol.query_cancel.get_first_ctaid.v4.b32.b128 {xdim, ydim, zdim, ignr} handle;

clusterlaunchcontrol.query_cancel.get_first_ctaid::x.b32.b128 reg0, handle;

clusterlaunchcontrol.query_cancel.get_first_ctaid::y.b32.b128 reg1, handle;

clusterlaunchcontrol.query_cancel.get_first_ctaid::z.b32.b128 reg2, handle;

9.7.16. Warp 级矩阵乘加指令

9.7.16.1. 矩阵形状

9.7.16.2. 矩阵数据类型

9.7.16.3. mma.sync 的块缩放

9.7.16.4. 使用 wmma 指令的矩阵乘加运算

9.7.16.4.1. WMMA 的矩阵片段

9.7.16.4.2. WMMA 的矩阵存储

9.7.16.4.3. Warp 级矩阵加载指令：wmma.load

.layout = {.row, .col}; .shape = {.m16n16k16, .m8n32k16, .m32n8k16}; .ss = {.global, .shared{::cta}}; .atype = {.f16, .s8, .u8}; .btype = {.f16, .s8, .u8}; .ctype = {.f16, .f32, .s32};

wmma.load.b.sync.aligned.m16n16k16.row.f16 {x0,x1,x2,x3,x4,x5,x,x7}, [ptr]; // Now use {x0, ..., x7} for the actual wmma.mma

// Load elements from f32 column-major matrix C and scale the values: .reg .b32 x<8>;

wmma.load.c.sync.aligned.m16n16k16.col.f32 {x0,x1,x2,x3,x4,x5,x6,x7}, [ptr];

mul.f32 x0, x0, 0.1; // repeat for all registers x<8>; ... mul.f32 x7, x7, 0.1; // Now use {x0, ..., x7} for the actual wmma.mma

// Load elements from integer matrix A: .reg .b32 x<4> // destination registers x<4> contain four packed .u8 values each wmma.load.a.sync.aligned.m32n8k16.row.u8 {x0,x1,x2,x3}, [ptr];

// Load elements from sub-byte integer matrix A: .reg .b32 x0; // destination register x0 contains eight packed .s4 values wmma.load.a.sync.aligned.m8n8k32.row.s4 {x0}, [ptr];

// Load elements from .bf16 matrix A: .reg .b32 x<4>; wmma.load.a.sync.aligned.m16n16k16.row.bf16 {x0,x1,x2,x3}, [ptr];

// Load elements from .tf32 matrix A: .reg .b32 x<4>; wmma.load.a.sync.aligned.m16n16k8.row.tf32 {x0,x1,x2,x3}, [ptr];

// Load elements from .f64 matrix A: .reg .b32 x<4>; wmma.load.a.sync.aligned.m8n8k4.row.f64 {x0}, [ptr];

9.7.16.4.4. Warp 级矩阵存储指令：wmma.store

.layout = {.row, .col}; .shape = {.m16n16k16, .m8n32k16, .m32n8k16}; .ss = {.global, .shared{::cta}}; .type = {.f16, .f32, .s32};

wmma.store.d.sync.aligned.layout.shape{.ss}.type [p], r {, stride} .layout = {.row, .col}; .shape = {.m8n8k32, .m8n8k128}; .ss = {.global, .shared{::cta}}; .type = {.s32};

wmma.store.d.sync.aligned.layout.shape{.ss}.type [p], r {, stride} .layout = {.row, .col}; .shape = {.m16n16k8}; .ss = {.global, .shared{::cta}}; .type = {.f32};

wmma.store.d.sync.aligned.layout.shape{.ss}.type [p], r {, stride} .layout = {.row, .col}; .shape = {.m8n8k4 }; .ss = {.global, .shared{::cta}}; .type = {.f64};

wmma.mma.sync.m16n16k16.row.col.f32.f32 {d0, d1, d2, d3, d4, d5, d6, d7}, ...; wmma.store.d.sync.m16n16k16.row.f32 [ptr], {d0, d1, d2, d3, d4, d5, d6, d7};

// Store s32 accumulator for m16n16k16 shape: .reg .b32 d<8>; wmma.store.d.sync.aligned.m16n16k16.row.s32 [ptr], {d0, d1, d2, d3, d4, d5, d6, d7};

// Store s32 accumulator for m8n8k128 shape: .reg .b32 d<2> wmma.store.d.sync.aligned.m8n8k128.row.s32 [ptr], {d0, d1};

// Store f64 accumulator for m8n8k4 shape: .reg .f64 d<2>; wmma.store.d.sync.aligned.m8n8k4.row.f64 [ptr], {d0, d1};

9.7.16.4.5. Warp 级矩阵乘累加指令：wmma.mma

// Integer (.u8/.s8 multiplicands) wmma.mma wmma.mma.sync.aligned.alayout.blayout.shape.s32.atype.btype.s32{.satfinite} d, a, b, c;

.alayout = {.row, .col}; .blayout = {.row, .col}; .shape = {.m16n16k16, .m8n32k16, .m32n8k16}; .dtype = {.f16, .f32}; .atype = {.s8, .u8}; .btype = {.s8, .u8}; .ctype = {.f16, .f32};

wmma.load.a.sync.aligned.m16n16k16.global.row.f16 {a0, a1, a2, a3, a4, a5, a6, a7}, [A]; wmma.load.b.sync.aligned.m16n16k16.global.col.f16 {b0, b1, b2, b3, b4, b5, b6, b7}, [B];

wmma.load.c.sync.aligned.m16n16k16.global.row.f32 {c0, c1, c2, c3, c4, c5, c6, c7}, [C];

wmma.mma.sync.aligned.m16n16k16.row.col.f32.f32 {d0, d1, d2, d3, d4, d5, d6, d7}, {a0, a1, a2, a3, a4, a5, a6, a7}, {b0, b1, b2, b3, b4, b5, b6, b7}, {c0, c1, c2, c3, c4, c5, c6, c7};

wmma.store.d.sync.aligned.m16n16k16.global.col.f32 [D], {d0, d1, d2, d3, d4, d5, d6, d7};

// Compute an integer WMMA: .reg .b32 a, b<4>; .reg .b32 c<8>, d<8>; wmma.mma.sync.aligned.m8n32k16.row.col.s32.s8.s8.s32 {d0, d1, d2, d3, d4, d5, d6, d7}, {a}, {b0, b1, b2, b3}, {c0, c1, c2, c3, c4, c5, c6, c7};

// Compute sub-byte WMMA: .reg .b32 a, b, c<2> d<2> wmma.mma.sync.aligned.m8n8k32.row.col.s32.s4.s4.s32 {d0, d1}, {a}, {b}, {c0, c1};

// Compute single-bit type WMMA: .reg .b32 a, b, c<2> d<2> wmma.mma.xor.popc.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32 {d0, d1}, {a}, {b}, {c0, c1};

// Compute double precision wmma .reg .f64 a, b, c<2>, d<2>; wmma.mma.sync.aligned.m8n8k4.row.col.f64.f64.f64.f64 {d0, d1}, {a}, {b}, {c0, c1};

// Compute alternate floating point precision wmma .reg .b32 a<2>, b<2>, c<8>, d<8>; wmma.mma.sync.aligned.m16n16k8.row.col.f32.tf32.tf32.f32 {d0, d1, d2, d3, d4, d5, d6, d7}, {a0, a1, a2, a3}, {b0, b1, b2, b3}, {c0, c1, c2, c3, c4, c5, c6, c7};

9.7.16.5. 使用 mma 指令的矩阵乘累加运算

9.7.16.5.1. mma.m8n8k4 使用 .f16 浮点类型的矩阵 Fragment

col = i for ai where i = {0,..,3}

col = %laneid % 4

col = i for bi where i = {0,..,3} if %laneid < 16 i+4 for bi where i = {0,..,3} otherwise

col = %laneid % 4 if %laneid < 16 (%laneid % 4) + 4 otherwise

col = i for ci where i = {0,..,7}

where X = (%laneid & 0b1) + (i & 0b10) for ci where i = {0,..,7}

col = (i & 0b100) + (%laneid & 0b10) + (i & 0b1) for ci where i = {0,..,7}

9.7.16.5.2. mma.m8n8k4 使用 .f64 浮点类型的矩阵 Fragment

col = %laneid % 4

col = %laneid >> 2

row = groupID

col = (threadID_in_group * 2) + (i & 0x1) for ci where i = {0, 1}

9.7.16.5.3. mma.m8n8k16 的矩阵 Fragment

row = groupID

col = (threadID_in_group * 4) + i for ai where i = {0,..,3}

row = (threadID_in_group * 4) + i for bi where i = {0,..,3}

col = groupID

row = groupID

col = (threadID_in_group * 2) + i for ci where i = {0, 1}

9.7.16.5.4. mma.m8n8k32 的矩阵 Fragment

row = groupID

col = (threadID_in_group * 8) + i for ai where i = {0,..,7}

row = (threadID_in_group * 8) + i for bi where i = {0,..,7}

col = groupID

row = groupID col = (threadID_in_group * 2) + i for ci where i = {0, 1}

9.7.16.5.5. mma.m8n8k128 的矩阵 Fragment

row = groupID

col = (threadID_in_group * 32) + i for ai where i = {0,..,31}

row = (threadID_in_group * 32) + i for bi where i = {0,..,31}

col = groupID

row = groupID

col = (threadID_in_group * 2) + i for ci where i = {0, 1}

9.7.16.5.6. mma.m16n8k4 的矩阵片段

row = groupID for a0 groupID + 8 for a1

col = threadID_in_group

row = groupID for a0 groupID + 8 for a1

col = threadID_in_group

row = threadID_in_group

col = groupID

row = threadID_in_group

col = groupID

row = groupID for c0 and c1 groupID + 8 for c2 and c3

col = (threadID_in_group * 2) + (i & 0x1) for ci where i = {0,..,3}

row = groupID for c0 and c1 groupID + 8 for c2 and c3

col = (threadID_in_group * 2) + (i & 0x1) for ci where i = {0,..,3}

9.7.16.5.7. mma.m16n8k8 的矩阵片段

row = groupID for a0 and a1 groupID + 8 for a2 and a3

col = threadID_in_group * 2 + (i & 0x1) for ai where i = {0,..,3}

row = groupID for a0 and a2 groupID + 8 for a1 and a3

col = threadID_in_group for a0 and a1 threadID_in_group + 4 for a2 and a3

row = groupID for a0 and a2 groupID + 8 for a1 and a3

col = threadID_in_group for a0 and a1 threadID_in_group + 4 for a2 and a3

row = (threadID_in_group * 2) + i for bi where i = {0, 1}

col = groupID

row = threadID_in_group for b0 threadID_in_group + 4 for b1

col = groupID

row = threadID_in_group for b0 threadID_in_group + 4 for b1

col = groupID

row = groupID for c0 and c1 groupID + 8 for c2 and c3

col = (threadID_in_group * 2) + (i & 0x1) for ci where i = {0,..,3}

row = groupID for c0 and c1 groupID + 8 for c2 and c3

col = (threadID_in_group * 2) + (i & 0x1) for ci where i = {0,..,3}

9.7.16.5.8. 浮点类型 mma.m16n8k16 的矩阵片段

row = groupID for ai where 0 <= i < 2 || 4 <= i < 6 groupID + 8 Otherwise

col = (threadID_in_group 2) + (i & 0x1) for ai where i < 4 (threadID_in_group 2) + (i & 0x1) + 8 for ai where i >= 4

row = groupID for ai where i % 2 = 0 groupID + 8 Otherwise

col = (i 2) + threadID_in_group for ai where i % 2 = 0 (i 2) - 2 + (threadID_in_group Otherwise

row = (threadID_in_group 2) + (i & 0x1) for bi where i < 2 (threadID_in_group 2) + (i & 0x1) + 8 for bi where i >= 2

col = groupID

row = threadID_in_group + (i * 4) for bi where i < 4

col = groupID

row = groupID for ci where i < 2 groupID + 8 for ci where i >= 2

col = (threadID_in_group * 2) + (i & 0x1) for ci where i = {0,..,3}

9.7.16.5.9. 整数类型 mma.m16n8k16 的矩阵片段

row = groupID for ai where i < 4 groupID + 8 for ai where i >= 4

col = (threadID_in_group * 4) + (i & 0x3) for ai where i = {0,..,7}

row = (threadID_in_group * 4) + i for bi where i = {0,..,3}

col = groupID

row = groupID for ci where i < 2 groupID + 8 for ci where i >= 2

col = (threadID_in_group * 2) + (i & 0x1) for ci where i = {0,..,3}

9.7.16.5.10. mma.m16n8k32 的矩阵片段

row = groupID for ai where i < 8 groupID + 8 for ai where i >= 8

col = (threadID_in_group * 8) + (i & 0x7) for ai where i = {0,..,15}

row = groupID for ai where 0 <= i < 4 || 8 <= i < 12 groupID + 8 otherwise

col = (threadID_in_group 4) + (i & 0x3) for ai where i < 8 (threadID_in_group 4) + (i & 0x3) + 16 for ai where i >= 8

row = (threadID_in_group * 8) + (i & 0x7) for bi where i = {0,..,7} col = groupID

row = (threadID_in_group 4) + (i & 0x3) for bi where i < 4 (threadID_in_group 4) + (i & 0x3) + 16 for bi where i >= 4

col = groupID

row = groupID for ci where i < 2 groupID + 8 for ci where i >= 2

col = (threadID_in_group * 2) + (i & 0x1) for ci where i = {0,..,3}

9.7.16.5.11. mma.m16n8k64 的矩阵片段

row = groupID for ai where 0 <= i < 8 || 16 <= i < 24 groupID + 8 otherwise

col = (threadID_in_group 8) + (i & 0x7) for ai where i < 16 (threadID_in_group 8) + (i & 0x7) + 32 for ai where i >= 16

row = (threadID_in_group 8) + (i & 0x7) for bi where i < 8 (threadID_in_group 8) + (i & 0x7) + 32 for bi where i >= 8

col = groupID

row = groupID for ci where i < 2 groupID + 8 for ci where i >= 2

col = (threadID_in_group * 2) + (i & 0x1) for ci where i = {0,..,3}

9.7.16.5.12. mma.m16n8k128 的矩阵片段

row = groupID for ai where i < 32 groupID + 8 for ai where i >= 32

col = (threadID_in_group * 32) + (i & 0x1F) for ai where i = {0, ...,63}

row = (threadID_in_group * 32) + i for bi where i = {0,...,31} col = groupID

row = groupID for ci where i < 2 groupID + 8 for ci where i >= 2

col = (threadID_in_group * 2) + (i & 0x1) for ci where i = {0, 1, 2, 3}

9.7.16.5.13. mma.m16n8k256 的矩阵片段

row = groupID for ai where 0 <= i < 32 || 64 <= i < 96 groupID + 8 otherwise

col = (threadID_in_group 32) + i for ai where i < 64 (threadID_in_group 32) + (i & 0x1F) + 128 for ai where i >= 64

row = (threadID_in_group 32) + (i & 0x1F) for bi where i < 32 (threadID_in_group 32) + (i & 0x1F) + 128 for bi where i >= 32

col = groupID

row = groupID for ci where i < 2 groupID + 8 for ci where i >= 2

col = (threadID_in_group * 2) + (i & 0x1) for ci where i = {0, 1, 2, 3}

9.7.16.5.14. 乘加指令：mma

.alayout = {.row, .col}; .blayout = {.row, .col}; .ctype = {.f16, .f32}; .dtype = {.f16, .f32};

.atype = {.bf16, .tf32}; .btype = {.bf16, .tf32}; .f8type = {.e4m3, .e5m2}; .f8f6f4type = {.e4m3, .e5m2, .e3m2, .e2m3, .e2m1}; .ctype = {.f16, .f32}; .dtype = {.f16, .f32}; .shape = {.m16n8k16, .m16n8k32}; .kind = {.kind::f8f6f4};

.kind = {.kind::mxf4}; .scale_vec_size = {.scale_vec::2X}; .stype = {.ue8m0};

mma.sync.aligned.m16n8k64.row.col.kind.block_scale.scale_vec_size.f32.e2m1.e2m1.f32.stype d, a, b, c, scale-a-data, {byte-id-a, thread-id-a}, scale-b-data, {byte-id-b, thread-id-b};

.kind = {.kind::mxf4nvf4}; .scale_vec_size = {.scale_vec::2X, .scale_vec::4X}; .stype = {.ue8m0, .ue4m3};

mma.sync.aligned.m16n8k32.row.col.kind.block_scale{.scale_vec_size}.f32.f8f6f4type.f8f6f4type.f32.stype d, a, b, c, scale-a-data, {byte-id-a, thread-id-a}, scale-b-data, {byte-id-b, thread-id-b};

.kind = {.kind::mxf8f6f4}; .scale_vec_size = {.scale_vec::1X}; .f8f6f4type = {.e4m3, .e5m2, .e3m2, .e2m3, .e2m1}; .stype = {.ue8m0};

.shape = {.m8n84, .m16n8k4, .m16n8k8, .m16n8k16};

.shape = {.m8n8k16, .m16n8k16, .m16n8k32} .atype = {.u8, .s8}; .btype = {.u8, .s8};

mma.sync.aligned.shape.row.col{.satfinite}.s32.atype.btype.s32 d, a, b, c;

.shape = {.m8n8k32, .m16n8k32, .m16n8k64} .atype = {.u4, .s4}; .btype = {.u4, .s4};

.bitOp = {.xor, .and} .shape = {.m8n8k128, .m16n8k128, .m16n8k256}

// f16 elements in C and f32 elements in D .reg .f16x2 %Ra<2> %Rb<2> %Rc<4> .reg .f32 %Rd<8> mma.sync.aligned.m8n8k4.row.col.f32.f16.f16.f16 {%Rd0, %Rd1, %Rd2, %Rd3, %Rd4, %Rd5, %Rd6, %Rd7}, {%Ra0, %Ra1}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3};

// f32 elements in C and D .reg .f16x2 %Ra<2>, %Rb<1>; .reg .f32 %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k8.row.col.f32.f16.f16.f32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1}, {%Rb0}, {%Rc0, %Rc1, %Rc2, %Rc3};

.reg .f16x2 %Ra<4>, %Rb<2>, %Rc<2>, %Rd<2>; mma.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 {%Rd0, %Rd1}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1}, {%Rc0, %Rc1};

.reg .f16 %Ra<4>, %Rb<2>; .reg .f32 %Rc<2>, %Rd<2>; mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3};

.reg .f16x2 %Ra<2>, %Rb<1>; .reg .f32 %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k8.row.col.f32.bf16.bf16.f32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1}, {%Rb0}, {%Rc0, %Rc1, %Rc2, %Rc3};

.reg .b32 %Ra<2>, %Rb<1>; .reg .f32 %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Rb2, %Rb3}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3};

.reg .f16x2 %Ra<2>, %Rb<1>; .reg .f32 %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3};

.reg .b32 %Ra<4>, %Rb<4>; .reg .f32 %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e5m2.f32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3};

.reg .b32 %Ra<4>, %Rb<4>; .reg .f32 %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k16.row.col.f32.e5m2.e4m3.f32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1}, {%Rb0}, {%Rc0, %Rc1, %Rc2, %Rc3};

.reg .b32 %Ra<4>, %Rb<4>; .reg .b32 %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k32.row.col.f16.e4m3.e5m2.f16 {%Rd0, %Rd1}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1}, {%Rc0, %Rc1};

.reg .b32 %Ra<4>, %Rb<4>; .reg .b32 %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k16.row.col.f16.e5m2.e5m2.f16 {%Rd0, %Rd1}, {%Ra0, %Ra1}, {%Rb0}, {%Rc0, %Rc1};

.reg .b32 %Ra<4>, %Rb<4>; .reg .f32 %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3};

.reg .b32 %Ra<4>, %Rb<4>; .reg .b32 %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k32.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16 {%Rd0, %Rd1}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1}, {%Rc0, %Rc1};

// s8 elements in A and u8 elements in B mma.sync.aligned.m8n8k16.row.col.satfinite.s32.s8.u8.s32 {%Rd0, %Rd1}, {%Ra}, {%Rb}, {%Rc0, %Rc1};

// u4 elements in A and B matrix mma.sync.aligned.m8n8k32.row.col.satfinite.s32.u4.u4.s32 {%Rd0, %Rd1}, {%Ra}, {%Rb}, {%Rc0, %Rc1};

// s8 elements in A and u8 elements in B .reg .b32 %Ra<2>, %Rb, %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k16.row.col.satfinite.s32.s8.u8.s32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1}, {%Rb}, {%Rc0, %Rc1, %Rc2, %Rc3};

// u4 elements in A and s4 elements in B .reg .b32 %Ra<2>, %Rb, %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k32.row.col.satfinite.s32.u4.s4.s32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1}, {%Rb}, {%Rc0, %Rc1, %Rc2, %Rc3};

// s8 elements in A and s8 elements in B .reg .b32 %Ra<4>, %Rb<2>, %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3};

// u8 elements in A and u8 elements in B .reg .b32 %Ra<4>, %Rb<2>, %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1 }, {%Rc0, %Rc1, %Rc2, %Rc3};

// b1 elements in A and B .reg .b32 %Ra, %Rb, %Rc<2>, %Rd<2>; mma.sync.aligned.m8n8k128.row.col.s32.b1.b1.s32.xor.popc {%Rd0, %Rd1}, {%Ra}, {%Rb}, {%Rc0, %Rc1};

.reg .b32 %Ra<2>, %Rb, %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.xor.popc {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1}, {%Rb}, {%Rc0, %Rc1, %Rc2, %Rc3};

.reg .b32 %Ra<2>, %Rb, %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k128.row.col.s32.b1.b1.s32.and.popc {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1}, {%Rb}, {%Rc0, %Rc1, %Rc2, %Rc3};

.reg .b32 %Ra<4>, %Rb<2>, %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.xor.popc {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3};

.reg .b32 %Ra<4>, %Rb<2>, %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k256.row.col.s32.b1.b1.s32.and.popc {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3};

.reg .f64 %Ra<8>, %Rb<4>, %Rc<4>, %Rd<4>; mma.sync.aligned.m16n8k4.row.col.f64.f64.f64.f64.rn {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1}, {%Rb0}, {%Rc0, %Rc1, %Rc2, %Rc3};

mma.sync.aligned.m16n8k8.row.col.f64.f64.f64.f64.rn {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3};

mma.sync.aligned.m16n8k16.row.col.f64.f64.f64.f64.rn {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3, %Ra4, %Ra5, %Ra6, %Ra7}, {%Rb0, %Rb1, %Rb2, %Rb3}, {%Rc0, %Rc1, %Rc2, %Rc3};

.reg .b32 %Ra<4>, %Rb<4>; .reg .f32 %Rc<4>, %Rd<4>; .reg .b32 scaleAData, scaleBData; .reg .u16 bidA, bidB, tidA, tidB; mma.sync.aligned.m16n8k64.row.col.kind::mxf4nvf4.block_scale.scale_vec::4X.f32.e2m1.e2m1.f32.ue4m3 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3}, scaleAData, {bidA, tidA}, scaleBData, {bidB, tidB};

.reg .b32 %Ra<4>, %Rb<4>; .reg .f32 %Rc<4>, %Rd<4>; .reg .b32 scaleAData, scaleBData; .reg .u16 bidA, bidB, tidA, tidB; mma.sync.aligned.m16n8k64.row.col.kind::mxf4nvf4.block_scale.scale_vec::4X.f32.e2m1.e2m1.f32.ue8m0 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3}, scaleAData, {bidA, tidA}, scaleBData, {bidB, tidB};

.reg .b32 %Ra<4>, %Rb<4>; .reg .f32 %Rc<4>, %Rd<4>; .reg .b32 scaleAData, scaleBData; mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.scale_vec::1X.f32.e3m2.e2m1.f32.ue8m0 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3}, scaleAData, {0, 1}, scaleBData, {0, 1};

.reg .b32 %Ra<4>, %Rb<4>; .reg .f32 %Rc<4>, %Rd<4>; .reg .b32 scaleAData, scaleBData; mma.sync.aligned.m16n8k32.row.col.kind::mxf8f6f4.block_scale.scale_vec::1X.f32.e4m3.e5m2.f32.ue8m0 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3}, scaleAData, {0, 1}, scaleBData, {0, 0};

9.7.16.5.15. Warp 级矩阵加载指令：ldmatrix

ldmatrix.sync.aligned.m8n16.num{.ss}.dst_fmt.src_fmt r, [p]; ldmatrix.sync.aligned.m16n16.num.trans{.ss}.dst_fmt.src_fmt r, [p];

ldmatrix.sync.aligned.m8n16.num{.ss}.dtype.ctype r, [p];

.shape = {.m8n8, .m16n16}; .num = {.x1, .x2, .x4}; .ss = {.shared{::cta}}; .type = {.b16, .b8}; .dst_fmt = { .b8x16 }; .src_fmt = { .b6x16_p32, .b4x16_p64 }; .dtype = { .s8 }; .ctype = { .s4 };

// Load two 8x8 matrices in column-major format .reg .b64 addr; .reg .b32 d<2>; ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16 {d0, d1}, [addr];

// Load four 8x8 matrices .reg .b64 addr; .reg .b32 d<4>; ldmatrix.sync.aligned.m8n8.x4.b16 {d0, d1, d2, d3}, [addr];

// Load one 16x16 matrices of 64-bit elements and transpose them .reg .b64 addr; .reg .b32 d<2>; ldmatrix.sync.aligned.m16n16.x1.trans.shared.b8 {d0, d1}, [addr];

// Load two 16x16 matrices of 64-bit elements and transpose them .reg .b64 addr; .reg .b32 d<4>; ldmatrix.sync.aligned.m16n16.x2.trans.shared::cta.b8 {d0, d1, d2, d3}, [addr];

// Load two 16x16 matrices of 6-bit elements and transpose them .reg .b64 addr; .reg .b32 d<4>; ldmatrix.sync.aligned.m16n16.x2.trans.shared::cta.b8x16.b6x16_p32 {d0, d1, d2, d3}, [addr];

// Load one 8x16 matrix of 4-bit signed elements expanded to 8-bit signed .reg .b64 addr; .reg .b32 d; ldmatrix.sync.aligned.m8n16.x1.shared::cta.s8.s4 {d}, [addr];

9.7.16.5.16. Warp 级矩阵存储指令：stmatrix

.shape = {.m8n8, .m16n8}; .num = {.x1, .x2, .x4}; .ss = {.shared{::cta}}; .type = {.b16, .b8};

// Store two 8x8 matrices in column-major format .reg .b64 addr; .reg .b32 r<2>; stmatrix.sync.aligned.m8n8.x2.trans.shared::cta.b16 [addr], {r0, r1};

// Store four 8x8 matrices .reg .b64 addr; .reg .b32 r<4>; stmatrix.sync.aligned.m8n8.x4.b16 [addr], {r0, r1, r2, r3};

// Store a single 16x8 matrix using generic addressing .reg .b64 addr; .reg .b32 r; stmatrix.sync.aligned.m16n8.x1.trans.shared.b8 [addr], {r};

// Store two 16x8 matrices .reg .b64 addr; .reg .b32 r<2>; stmatrix.sync.aligned.m16n8.x2.trans.shared::cta.b8 [addr],{r0, r1};

// Store four 16x8 matrices .reg .b64 addr; .reg .b32 r<4>; stmatrix.sync.aligned.m16n8.x4.b8 [addr], {r0, r1, r2, r3};

9.7.16.5.17. Warp 级矩阵转置指令：movmatrix

.shape = {.m8n8}; .type = {.b16};

9.7.16.6. 使用 mma.sp 指令的稀疏矩阵乘加运算

9.7.16.6.1. 稀疏矩阵存储

9.7.16.6.2. 稀疏矩阵 A 乘加运算的矩阵片段

9.7.16.6.2.1. 稀疏 mma.m16n8k16 的矩阵片段（.f16 与 .bf16 类型）

row = groupID for a0 and a1 groupID + 8 for a2 and a3

col = [firstcol ... lastcol] // As per the mapping of non-zero elements // as described in Sparse matrix storage

Where firstcol = threadID_in_group * 4 lastcol = firstcol + 3

9.7.16.6.2.2. 稀疏 mma.m16n8k32 的矩阵片段（.f16 与 .bf16 类型）

row = groupID for ai where 0 <= i < 2 || 4 <= i < 6 groupID + 8 Otherwise

col = [firstcol ... lastcol] // As per the mapping of non-zero elements // as described in Sparse matrix storage

Where firstcol = threadID_in_group 4 For ai where i < 4 (threadID_in_group 4) + 16 for ai where i >= 4 lastcol = firstcol + 3

9.7.16.6.2.3. 稀疏 mma.m16n8k16 的矩阵片段（.tf32 浮点类型）

row = groupID for a0 and a2 groupID + 8 for a1 and a3

col = [firstcol ... lastcol] // As per the mapping of non-zero elements // as described in Sparse matrix storage

Where firstcol = threadID_in_group 2 for a0 and a1 (threadID_in_group 2) + 8 for a2 and a3 lastcol = firstcol + 1

9.7.16.6.2.4. 稀疏 mma.m16n8k8 的矩阵片段（.tf32 浮点类型）

row = groupID for a0 groupID + 8 for a1

col = [firstcol ... lastcol] // As per the mapping of non-zero elements // as described in Sparse matrix storage

Where firstcol = threadID_in_group * 2 lastcol = firstcol + 1

9.7.16.6.2.5. 稀疏 mma.m16n8k32 的矩阵片段（.u8 / .s8 整数类型）

row = groupID for ai where 0 <= i < 4 groupID + 8 Otherwise

col = [firstcol ... lastcol] // As per the mapping of non-zero elements // as described in Sparse matrix storage

Where firstcol = threadID_in_group * 8 lastcol = firstcol + 7

9.7.16.6.2.6. 稀疏 mma.m16n8k64 的矩阵片段（.u8 / .s8 / .e4m3 / .e5m2 类型）

row = groupID for ai where 0 <= i < 4 || 8 <= i < 12 groupID + 8 Otherwise

col = [firstcol ... lastcol] // As per the mapping of non-zero elements // as described in Sparse matrix storage

Where firstcol = threadID_in_group 8 For ai where i < 8 (threadID_in_group 8) + 32 For ai where i >= 8 lastcol = firstcol + 7

9.7.16.6.2.7. .u4 / .s4 整数类型稀疏 mma.m16n8k64 的矩阵片段

row = groupID for ai where 0 <= i < 8 groupID + 8 Otherwise

col = [firstcol ... lastcol] // As per the mapping of non-zero elements // as described in Sparse matrix storage

Where firstcol = threadID_in_group * 16 lastcol = firstcol + 15

9.7.16.6.2.8. .u4 / .s4 整数类型稀疏 mma.m16n8k128 的矩阵片段

row = groupID for ai where 0 <= i < 8 || 16 <= i < 24 groupID + 8 Otherwise

col = [firstcol ... lastcol] // As per the mapping of non-zero elements // as described in Sparse matrix storage

Where firstcol = threadID_in_group 16 For ai where i < 16 (threadID_in_group 16) + 64 For ai where i >= 16 lastcol = firstcol + 15

9.7.16.6.3. 乘加指令：mma.sp / mma.sp::ordered_metadata

.ctype = {.f16, .f32}; .dtype = {.f16, .f32}; .spvariant = {.sp, .sp::ordered_metadata};

.f8type = {.e4m3, .e5m2}; .spvariant = {.sp, .sp::ordered_metadata}; .f8f6f4type = {.e4m3, .e5m2, .e3m2, .e2m3, .e2m1}; .kind = {kind::f8f6f4}; .ctype = {.f16, .f32}; .dtype = {.f16, .f32};

.spvariant = {.sp::ordered_metadata}; .kind = {.kind::mxf4}; .scale_vec_size = {.scale_vec::2X}; .stype = {.ue8m0};

mma.spvariant.sync.aligned.m16n8k128.row.col.kind.block_scale.scale_vec_size.f32.e2m1.e2m1.f32.stype d, a, b, c, e, f, scale-a-data, {byte-id-a, thread-id-a}, scale-b-data, {byte-id-b, thread-id-b};

.spvariant = {.sp::ordered_metadata}; .kind = {.kind::mxf4nvf4}; .scale_vec_size = {.scale_vec::2X, .scale_vec::4X}; .stype = {.ue8m0, .ue4m3};

mma.spvariant.sync.aligned.m16n8k64.row.col.kind.block_scale{.scale_vec_size}.f32.f8f6f4type.f8f6f4type.f32.stype d, a, b, c, e, f, scale-a-data, {byte-id-a, thread-id-a}, scale-b-data, {byte-id-b, thread-id-b};

.spvariant = {.sp::ordered_metadata}; .kind = {.kind::mxf8f6f4}; .scale_vec_size = {.scale_vec::1X}; .f8f6f4type = {.e4m3, .e5m2, .e3m2, .e2m3, .e2m1}; .stype = {.ue8m0};

.shape = {.m16n8k32, .m16n8k64} .atype = {.u8, .s8}; .btype = {.u8, .s8}; .spvariant = {.sp, .sp::ordered_metadata};

mma.spvariant.sync.aligned.shape.row.col{.satfinite}.s32.atype.btype.s32 d, a, b, c, e, f;

.shape = {.m16n8k64, .m16n8k128} .atype = {.u4, .s4}; .btype = {.u4, .s4}; .spvariant = {.sp, .sp::ordered_metadata};

.reg .f16x2 %Ra<2> %Rb<2> %Rc<2> %Rd<2> .reg .b32 %Re;

mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 {%Rd0, %Rd1}, {%Ra0, %Ra1}, {%Rb0, %Rb1}, {%Rc0, %Rc1}, %Re, 0x1;

.reg .b32 %Ra<2>, %Rb<2>; .reg .f32 %Rc<4>, %Rd<4>; .reg .b32 %Re; mma.sp.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3}, %Re, 0x1;

.reg .b32 %Ra<4>, %Rb<4>; .reg .f32 %Rc<4>, %Rd<4>; .reg .b32 %Re; mma.sp.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1, %Rb2, %Rb3}, {%Rc0, %Rc1, %Rc2, %Rc3}, %Re, 0x1;

.reg .b32 %Ra<4>, %Rb<4>; .reg .f32 %Rc<4>, %Rd<4>; .reg .b32 %Re; mma.sp.sync.aligned.m16n8k64.row.col.f32.e5m2.e4m3.f32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1, %Rb2, %Rb3}, {%Rc0, %Rc1, %Rc2, %Rc3}, %Re, 0;

.reg .b32 %Ra<2>, %Rb<2>; .reg .f32 %Rc<4>, %Rd<4>; .reg .b32 %Re; mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3}, %Re, 0x1;

.reg .b32 %Ra<4>, %Rb<4>; .reg .f32 %Rc<4>, %Rd<4>; .reg .b32 %Re; mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1, %Rb2, %Rb3}, {%Rc0, %Rc1, %Rc2, %Rc3}, %Re, 0;

.reg .b32 %Ra<4>, %Rb<4>; .reg .b32 %Rc<4>, %Rd<4>; .reg .b32 %Re; mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16 {%Rd0, %Rd1}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1, %Rb2, %Rb3}, {%Rc0, %Rc1}, %Re, 0;

// u8 elements in A and B matrix mma.sp.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3}, %Re, 0x1;

// s8 elements in A and B matrix mma.sp.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1, %Rb2, %Rb3}, {%Rc0, %Rc1, %Rc2, %Rc3}, %Re, 0x0;

// s8 elements in A and B matrix with ordered metadata mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1, %Rb2, %Rb3}, {%Rc0, %Rc1, %Rc2, %Rc3}, %Re, 0x0;

// u4 elements in A and B matrix mma.sp.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1}, {%Rb0, %Rb1}, {%Rc0, %Rc1, %Rc2, %Rc3}, %Re, 0x1;

// u4 elements in A and B matrix mma.sp.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1, %Rb2, %Rb3}, {%Rc0, %Rc1, %Rc2, %Rc3}, %Re, 0x0;

.reg .b32 %Ra<4>, %Rb<4>; .reg .f32 %Rc<4>, %Rd<4>; .reg .b32 scaleAData, scaleBData; .reg .u16 bidA, bidB, tidA, tidB; .reg .b32 %Re; mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.kind::mxf4nvf4.block_scale.scale_vec::4X.f32.e2m1.e2m1.f32.ue4m3 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1, %Rb2, %Rb3}, {%Rc0, %Rc1, %Rc2, %Rc3}, %Re, 0, scaleAData, {bidA, tidA}, scaleBData, {bidB, tidB};

.reg .b32 %Ra<4>, %Rb<4>; .reg .f32 %Rc<4>, %Rd<4>; .reg .b32 scaleAData, scaleBData; .reg .u16 bidA, bidB, tidA, tidB; .reg .b32 %Re; mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.kind::mxf4nvf4.block_scale.scale_vec::4X.f32.e2m1.e2m1.f32.ue8m0 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1, %Rb2, %Rb3}, {%Rc0, %Rc1, %Rc2, %Rc3}, %Re, 0, scaleAData, {bidA, tidA}, scaleBData, {bidB, tidB};

.reg .b32 %Ra<4>, %Rb<4>; .reg .f32 %Rc<4>, %Rd<4>; .reg .b32 scaleAData, scaleBData; .reg .b32 %Re; mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::mxf8f6f4.block_scale.scale_vec::1X.f32.e3m2.e2m1.f32.ue8m0 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1, %Rb2, %Rb3}, {%Rc0, %Rc1, %Rc2, %Rc3}, %Re, 0, scaleAData, {0, 1}, scaleBData, {0, 1};

.reg .b32 %Ra<4>, %Rb<4>; .reg .f32 %Rc<4>, %Rd<4>; .reg .b32 scaleAData, scaleBData; .reg .b32 %Re; mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::mxf8f6f4.block_scale.scale_vec::1X.f32.e4m3.e5m2.f32.ue8m0 {%Rd0, %Rd1, %Rd2, %Rd3}, {%Ra0, %Ra1, %Ra2, %Ra3}, {%Rb0, %Rb1, %Rb2, %Rb3}, {%Rc0, %Rc1, %Rc2, %Rc3}, %Re, 0, scaleAData, {0, 1}, scaleBData, {0, 0};

9.7.17. 异步 Warpgroup 级矩阵乘加指令

9.7.17.1. Warpgroup

9.7.17.2. 矩阵形状

9.7.17.3. 矩阵数据类型

9.7.17.4. 异步代理

9.7.17.5. 使用 wgmma.mma_async 指令的异步 Warpgroup 级矩阵乘累加运算

9.7.17.5.1. 寄存器片段与共享内存矩阵布局

9.7.17.5.1.1. 寄存器片段

9.7.17.5.1.1.1. wgmma.mma_async.m64nNk16 的矩阵片段

9.7.17.5.1.1.2. wgmma.mma_async.m64nNk8 的矩阵片段

9.7.17.5.1.1.3. wgmma.mma_async.m64nNk32 的矩阵片段

9.7.17.5.1.1.4. wgmma.mma_async.m64nNk256 的矩阵片段

9.7.17.5.1.2. 共享内存矩阵布局

9.7.17.5.1.2.1. Stride 支持的主序性

9.7.17.5.1.2.1.1. 前导维度字节偏移

9.7.17.5.1.2.1.2. Stride 维度字节偏移

9.7.17.5.1.2.1.3. 规范布局

9.7.17.5.1.2.2. 矩阵描述符格式

9.7.17.5.2. 异步乘加指令：wgmma.mma_async

wgmma.mma_async.sync.aligned.shape.dtype.f16.f16 d, a, b-desc, scale-d, imm-scale-a, imm-scale-b, imm-trans-b;

.shape = {.m64n8k16, .m64n16k16, .m64n24k16, .m64n32k16, .m64n40k16, .m64n48k16, .m64n56k16, .m64n64k16, .m64n72k16, .m64n80k16, .m64n88k16, .m64n96k16, .m64n104k16, .m64n112k16, .m64n120k16, .m64n128k16, .m64n136k16, .m64n144k16, .m64n152k16, .m64n160k16, .m64n168k16, .m64n176k16, .m64n184k16, .m64n192k16, .m64n200k16, .m64n208k16, .m64n216k16, .m64n224k16, .m64n232k16, .m64n240k16, .m64n248k16, .m64n256k16}; .dtype = {.f16, .f32};

wgmma.mma_async.sync.aligned.shape.dtype.bf16.bf16 d, a-desc, b-desc, scale-d, imm-scale-a, imm-scale-b, imm-trans-a, imm-trans-b;

wgmma.mma_async.sync.aligned.shape.dtype.bf16.bf16 d, a, b-desc, scale-d, imm-scale-a, imm-scale-b, imm-trans-b;

.tf32 floating point type:

wgmma.mma_async.sync.aligned.shape.dtype.tf32.tf32 d, a-desc, b-desc, scale-d, imm-scale-a, imm-scale-b;

wgmma.mma_async.sync.aligned.shape.dtype.tf32.tf32 d, a, b-desc, scale-d, imm-scale-a, imm-scale-b;

.shape = {.m64n8k8, .m64n16k8, .m64n24k8, .m64n32k8, .m64n40k8, .m64n48k8, .m64n56k8, .m64n64k8, .m64n72k8, .m64n80k8, .m64n88k8, .m64n96k8, .m64n104k8, .m64n112k8, .m64n120k8, .m64n128k8, .m64n136k8, .m64n144k8, .m64n152k8, .m64n160k8, .m64n168k8, .m64n176k8, .m64n184k8, .m64n192k8, .m64n200k8, .m64n208k8, .m64n216k8, .m64n224k8, .m64n232k8, .m64n240k8, .m64n248k8, .m64n256k8}; .dtype = {.f32};

FP8 floating point type

wgmma.mma_async.sync.aligned.shape.dtype.atype.btype d, a-desc, b-desc, scale-d, imm-scale-a, imm-scale-b;

wgmma.mma_async.sync.aligned.shape.dtype.atype.btype d, a, b-desc, scale-d, imm-scale-a, imm-scale-b;

.shape = {.m64n8k32, .m64n16k32, .m64n24k32, .m64n32k32, .m64n40k32, .m64n48k32, .m64n56k32, .m64n64k32, .m64n72k32, .m64n80k32, .m64n88k32, .m64n96k32, .m64n104k32, .m64n112k32, .m64n120k32, .m64n128k32, .m64n136k32, .m64n144k32, .m64n152k32, .m64n160k32, .m64n168k32, .m64n176k32, .m64n184k32, .m64n192k32, .m64n200k32, .m64n208k32, .m64n216k32, .m64n224k32, .m64n232k32, .m64n240k32, .m64n248k32, .m64n256k32}; .atype = {.e4m3, .e5m2}; .btype = {.e4m3, .e5m2}; .dtype = {.f16, .f32};

wgmma.mma_async.sync.aligned.shape{.satfinite}.s32.atype.btype d, a, b-desc, scale-d;

.shape = {.m64n8k32, .m64n16k32, .m64n24k32, .m64n32k32, .m64n48k32, .m64n64k32, .m64n80k32, .m64n96k32, .m64n112k32, .m64n128k32, .m64n144k32, .m64n160k32, .m64n176k32, .m64n192k32, .m64n208k32, .m64n224k32}; .atype = {.s8, .u8}; .btype = {.s8, .u8};

wgmma.mma_async.sync.aligned.shape.s32.b1.b1.op.popc d, a, b-desc, scale-d;

.shape = {.m64n8k256, .m64n16k256, .m64n24k256, .m64n32k256, .m64n48k256, .m64n64k256, .m64n80k256, .m64n96k256, .m64n112k256, .m64n128k256, .m64n144k256, .m64n160k256, .m64n176k256, .m64n192k256, .m64n208k256, .m64n224k256, .m64n240k256, .m64n256k256}; .op = {.and};

wgmma.mma_async.sync.aligned.m64n72k16.f16.f16.f16 {f16d0, f16d1, f16d2, f16d3, f16d4, f16d5, f16d6, f16d7, f16d8, f16d9, f16d10, f16d11, f16d12, f16d13, f16d14, f16d15, f16d16, f16d17}, descA, descB, scaleD, -1, 1, 1, 0;

wgmma.mma_async.sync.aligned.m64n120k16.f32.bf16.bf16 {f32d0, f32d1, f32d2, f32d3, f32d4, f32d5, f32d6, f32d7, f32d8, f32d9, f32d10, f32d11, f32d12, f32d13, f32d14, f32d15, f32d16, f32d17, f32d18, f32d19, f32d20, f32d21, f32d22, f32d23, f32d24, f32d25, f32d26, f32d27, f32d28, f32d29, f32d30, f32d31, f32d32, f32d33, f32d34, f32d35, f32d36, f32d37, f32d38, f32d39, f32d40, f32d41, f32d42, f32d43, f32d44, f32d45, f32d46, f32d47, f32d48, f32d49, f32d50, f32d51, f32d52, f32d53, f32d54, f32d55, f32d56, f32d57, f32d58, f32d59}, {bf16a0, bf16a1, bf16a2, bf16a3}, descB, scaleD, -1, -1, 0;

.reg .f32 f32d<40>; .reg .b64 descA, descB;

wgmma.mma_async.sync.aligned.m64n16k8.f32.tf32.tf32 {f32d0, f32d1, f32d2, f32d3, f32d4, f32d5, f32d6, f32d7}, descA, descB, 0, -1, -1;

.reg .b32 f16d<8>, f16a<8>; .reg .f32 f32d<8>; .reg .b64 descA, descB;

wgmma.mma_async.sync.aligned.m64n8k32.f16.e4m3.e5m2 {f16d0, f16d1}, descA, descB, scaleD, -1, 1;

wgmma.mma_async.sync.aligned.m64n8k32.f32.e5m2.e4m3 {f32d0, f32d1, f32d2, f32d3}, {f16a0, f16a1, f16a2, f16a3}, descB, 1, -1, -1;

wgmma.mma_async.sync.aligned.m64n8k32.s32.s8.s8.satfinite {s32d0, s32d1, s32d2, s32d3}, {s32a0, s32a1, s32a2, s32a3}, descB, 1;

wgmma.mma_async.sync.aligned.m64n8k32.s32.u8.u8 {s32d0, s32d1, s32d2, s32d3}, descA, descB, scaleD;

wgmma.mma_async.sync.aligned.m64n8k32.s32.s8.u8.satfinite {s32d0, s32d1, s32d2, s32d3}, {s32a0, s32a1, s32a2, s32a3}, descB, scaleD;

wgmma.mma_async.sync.aligned.m64n8k32.s32.u8.s8 {s32d0, s32d1, s32d2, s32d3}, descA, descB, scaleD;

wgmma.mma_async.sync.aligned.m64n8k256.s32.b1.b1.and.popc {s32d0, s32d1, s32d2, s32d3}, {b32a0, b32a1, b32a2, b32a3}, descB, scaleD;

9.7.17.6. 使用 wgmma.mma_async.sp 指令的异步 Warpgroup 级乘加运算

9.7.17.6.1. 稀疏矩阵存储

9.7.17.6.2. 稀疏矩阵 A 的 warpgroup 级乘加运算的矩阵片段

9.7.17.6.2.1. 稀疏 wgmma.mma_async.m64nNk32 的矩阵片段

9.7.17.6.2.2. 稀疏 wgmma.mma_async.m64nNk16 的矩阵片段

9.7.17.6.2.3. 稀疏 wgmma.mma_async.m64nNk64 的矩阵片段

9.7.17.6.3. 异步乘加指令：wgmma.mma_async.sp

wgmma.mma_async.sp.sync.aligned.shape.dtype.f16.f16 d, a, b-desc, sp-meta, sp-sel, scale-d, imm-scale-a, imm-scale-b, imm-trans-b;

wgmma.mma_async.sp.sync.aligned.shape.dtype.bf16.bf16 d, a-desc, b-desc, sp-meta, sp-sel, scale-d, imm-scale-a, imm-scale-b, imm-trans-a, imm-trans-b;

wgmma.mma_async.sp.sync.aligned.shape.dtype.bf16.bf16 d, a, b-desc, sp-meta, sp-sel, scale-d, imm-scale-a, imm-scale-b, imm-trans-b;

.tf32 floating point type:

wgmma.mma_async.sp.sync.aligned.shape.dtype.tf32.tf32 d, a-desc, b-desc, sp-meta, sp-sel, scale-d, imm-scale-a, imm-scale-b;

wgmma.mma_async.sp.sync.aligned.shape.dtype.tf32.tf32 d, a, b-desc, sp-meta, sp-sel, scale-d, imm-scale-a, imm-scale-b;

FP8 floating point type

wgmma.mma_async.sp.sync.aligned.shape.dtype.atype.btype d, a-desc, b-desc, sp-meta, sp-sel, scale-d, imm-scale-a, imm-scale-b;

wgmma.mma_async.sp.sync.aligned.shape.dtype.atype.btype d, a, b-desc, sp-meta, sp-sel, scale-d, imm-scale-a, imm-scale-b;

.shape = {.m64n8k64, .m64n16k64, .m64n24k64, .m64n32k64, .m64n40k64, .m64n48k64, .m64n56k64, .m64n64k64, .m64n72k64, .m64n80k64, .m64n88k64, .m64n96k64, .m64n104k64, .m64n112k64, .m64n120k64, .m64n128k64, .m64n136k64, .m64n144k64, .m64n152k64, .m64n160k64, .m64n168k64, .m64n176k64, .m64n184k64, .m64n192k64, .m64n200k64, .m64n208k64, .m64n216k64, .m64n224k64, .m64n232k64, .m64n240k64, .m64n248k64, .m64n256k64}; .atype = {.e4m3, .e5m2}; .btype = {.e4m3, .e5m2}; .dtype = {.f16, .f32};

wgmma.mma_async.sp.sync.aligned.shape{.satfinite}.s32.atype.btype d, a, b-desc, sp-meta, sp-sel, scale-d;

.shape = {.m64n8k64, .m64n16k64, .m64n24k64, .m64n32k64, .m64n48k64, .m64n64k64, .m64n80k64, .m64n96k64, .m64n112k64, .m64n128k64, .m64n144k64, .m64n160k64, .m64n176k64, .m64n192k64, .m64n208k64, .m64n224k64, .m64n240k64, .m64n256k64}; .atype = {.s8, .u8}; .btype = {.s8, .u8};

9.7.17.7. 异步 wgmma 代理操作

9.7.17.7.1. 异步乘加指令：wgmma.fence

// Example 2, use-case with the input value updated in between: wgmma.fence.sync.aligned; wgmma.mma_async.sync.aligned.m64n8k32.s32.u8.u8 {s32d0, s32d1, s32d2, s32d3}, descA, descB, scaleD; ... mov.b32 s32d0, new_val; wgmma.fence.sync.aligned; wgmma.mma_async.sync.aligned.m64n8k32.s32.u8.u8 {s32d4, s32d5, s32d6, s32d7}, {s32d0, s32d1, s32d2, s32d3}, descB, scaleD; wgmma.commit_group.sync.aligned; wgmma.wait_group.sync.aligned 0;

9.7.17.7.2. 异步乘加指令：wgmma.commit_group

9.7.17.7.3. 异步乘加指令：wgmma.wait_group

wgmma.mma_async.sync.aligned.m64n8k32.s32.u8.u8 {s32d0, s32d1, s32d2, s32d3}, descA, descB, scaleD; wgmma.commit_group.sync.aligned;

wgmma.mma_async.sync.aligned.m64n8k16.f32.f16.f16 {f32d0, f32d1, f32d2, f32d3}, {f16a0, f16a1, f16a2, f16a3}, descB, 1, -1, -1, 1; wgmma.commit_group.sync.aligned;

wgmma.wait_group.sync.aligned 0;

9.7.18. TensorCore 第五代指令族

9.7.18.1. Tensor Memory

9.7.18.1.1. Tensor Memory 寻址

9.7.18.1.2. Tensor Memory 分配

9.7.18.2. 矩阵与数据移动形状

9.7.18.2.1. 矩阵形状

9.7.18.2.1.1. 目标 ISA 说明

9.7.18.2.2. 指定矩阵形状

9.7.18.2.3. 数据搬运形状

9.7.18.2.3.1. 内存布局

9.7.18.2.3.1.1. 形状 .32x32b 的矩阵片段

9.7.18.2.3.1.2. 形状 .16x64b 的矩阵片段

9.7.18.2.3.1.3. 形状 .16x128b 的矩阵片段

9.7.18.2.3.1.4. 形状 .16x256b 的矩阵片段

9.7.18.2.3.1.5. 形状 .16x32bx2 的矩阵片段

9.7.18.3. Strides 所支持的 Major-ness

9.7.18.3.1. Leading Dimension Stride：相对偏移或绝对地址

9.7.18.3.1.1. 相对偏移模式

9.7.18.3.1.2. K 维度为 48B 时的绝对地址模式

9.7.18.3.1.2.1. 对 Leading Dimension 绝对地址 Stride 的限制

9.7.18.3.2. Stride Dimension 字节偏移

9.7.18.3.3. 规范布局

9.7.18.4. 矩阵描述符

9.7.18.4.1. 共享内存描述符

9.7.18.4.1.1. 目标 ISA 说明

9.7.18.4.2. 指令描述符

9.7.18.4.2.1. 目标 ISA 说明

9.7.18.4.3. 零列掩码描述符

9.7.18.5. 发出粒度

9.7.18.5.1. CTA 对

9.7.18.5.2. 对等 CTA

9.7.18.6. 第五代 TensorCore 操作的内存一致性模型

9.7.18.6.1. 异步操作

9.7.18.6.2. 流水线化的 tcgen05 指令

9.7.18.6.2.1. 隐式流水线化的 tcgen05 指令

9.7.18.6.2.1.1. 基于 mbarrier 的完成机制

9.7.18.6.2.1.2. 基于 tcgen05.wait 指令的完成机制

9.7.18.6.3. tcgen05 指令的专用线程间同步

9.7.18.6.4. 规范同步模式

9.7.18.6.4.1. 流水线化指令，同一线程

9.7.18.6.4.2. 非流水线化指令，同一线程

9.7.18.6.4.3. 流水线化指令，同一 warp 中的不同线程

9.7.18.6.4.4. 非流水线化指令，不同线程

9.7.18.6.4.5. 寄存器依赖，同一线程

9.7.18.6.5. 共享内存访问

9.7.18.7. Tensor Memory 分配与管理指令

9.7.18.7.1. TensorCore 第五代指令：tcgen05.alloc 、 tcgen05.dealloc 、 tcgen05.relinquish_alloc_permit

tcgen05.dealloc{.exclusive}.cta_group.sync.aligned.b32 taddr, nCols;

tcgen05.relinquish_alloc_permit.cta_group.sync.aligned;

.cta_group = { .cta_group::1, .cta_group::2 }

tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [sMemAddr1], 32; ld.shared.b32 taddr, [sMemAddr1]; // use taddr ... // more allocations and its usages ... tcgen05.dealloc.cta_group::1.sync.aligned.b32 taddr, 32; // more deallocations ... tcgen05.relinquish_alloc_permit.cta_group::1.sync.aligned;

// Example 2: Exclusive allocation and deallocation for 2-CTA

// Following instructions are performed by current warp and the warp in the peer-CTA: tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32 [sMemAddr2], 32; ld.shared.b32 taddr, [sMemAddr2]; // use taddr ... // more allocations and its usages ... tcgen05.dealloc.cta_group::2.sync.aligned.b32 taddr, 32; // more deallocations ... tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned;

// Example 3: Exclusive allocation and deallocation for 2-CTA

.reg .b32 sMemAddr, taddr; .reg .u32 nCols;

mov.u32 nCols, 576;

tcgen05.alloc.exclusive.cta_group::2.sync.aligned.shared::cta.b32 [sMemAddr], nCols; // ... tcgen05.dealloc.exclusive.cta_group::2.sync.aligned.b32 taddr, nCols; // ... tcgen05.relinquish_alloc_permit.cta_group::2.sync.aligned;

9.7.18.8. Tensor Memory 与寄存器加载/存储指令

9.7.18.8.1. 访问限制

9.7.18.8.2. 打包与解包

9.7.18.8.3. TensorCore 第五代指令：tcgen05.ld

tcgen05.ld.sync.aligned.shape1.num{.pack}.b32 r, [taddr];

tcgen05.ld.sync.aligned.shape2.num{.pack}.b32 r, [taddr], immHalfSplitoff;

.shape1 = { .16x64b, .16x128b, .16x256b, .32x32b } .shape2 = { .16x32bx2 } .num = { .x1, .x2, .x4, .x8, .x16, .x32, .x64, .x128 } .pack = { .pack::16b }

// Floating point type load along with reduction :

tcgen05.ld.red.sync.aligned.shape3.num.redOp{.abs}{.NaN}.f32 r, redval, [taddr];

tcgen05.ld.red.sync.aligned.shape4.num.redOp{.abs}{.NaN}.f32 r, redval, [taddr], immHalfSplitoff;

// Integer type load along with reduction :

tcgen05.ld.red.sync.aligned.shape3.num.redOp.type r, redval, [taddr];

tcgen05.ld.red.sync.aligned.shape4.num.redOp.type r, redval, [taddr], immHalfSplitoff;

.shape3 = { .32x32b } .shape4 = { .16x32bx2 } .redOp = { .min, .max } .type = { .u32, .s32 }

tcgen05.ld.spcompress.sync.aligned.shape.num.rowop.spfactor{.abs}.type.idxsize mdata, cdata, [taddr];

tcgen05.ld.red.spcompress.sync.aligned.shape.num.rowop.spfactor{.abs}{.NaN}.type.idxsize mdata, cdata, redval, [taddr];

.shape = { .32x32b } .rowop = { .min, .max } .type = { .f32 } .idxsize = { .b2 } .spfactor = { .sp::2:4 } .num = { .x4, .x8, .x16, .x32, .x64, .x128 }

tcgen05.ld.sync.aligned.16x128b.x4.b32 {r0, r1, r2, r3, r4, r5, r6, r7}, [taddr2];

tcgen05.ld.red.sync.aligned.16x32bx2.x8.u32.max {r0, r1, r2, r3, r4, r5, r6, r7}, redVal, [taddr3], 16; tcgen05.ld.red.spcompress.sync.aligned.32x32b.x32.max.sp::2:4.abs.f32.b2 {mdata_0}, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15}, redval, [taddr];

9.7.18.8.4. TensorCore 第五代指令：tcgen05.st

tcgen05.st.sync.aligned.shape2.num{.unpack}.b32 [taddr], immHalfSplitoff, r;

.shape1 = { .16x64b, .16x128b, .16x256b, .32x32b } .shape2 = { .16x32bx2 } .num = { .x1, .x2, .x4, .x8, .x16, .x32, .x64, .x128 } .unpack = { .unpack::16b }

tcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32 [taddr1], {r0, r1};

9.7.18.8.5. TensorCore 第五代指令：tcgen05.wait

.wait_operation = { .wait::ld, .wait::st }

tcgen05.ld.sync.aligned.32x32b.x2.b32 {r0, r1}, [taddr0];

// Prevents subsequent tcgen05.mma from racing ahead of the tcgen05.ld

tcgen05.wait::ld.sync.aligned;

tcgen05.mma.cta_group::1.kind::f16 [taddr0], a-desc, b-desc, idesc, p;

Example 2:

tcgen05.st.sync.aligned.32x32b.x2.b32 [taddr0], {r0, r1};

// Prevents the write to taddr0 in tcgen05.mma from racing ahead of the tcgen05.st

tcgen05.wait::st.sync.aligned;

tcgen05.mma.cta_group::1.kind::f16 [taddr0], a-desc, b-desc, idesc, p;

9.7.18.9. Tensor Memory 数据移动指令

9.7.18.9.1. 可选解压缩

9.7.18.9.1.1. 将 4 位浮点解压缩为 8 位类型

9.7.18.9.1.2. 将 6 位浮点解压缩为 8 位类型

9.7.18.9.2. TensorCore 第五代指令：tcgen05.cp

.cta_group = { .cta_group::1, .cta_group::2 } .src_fmt = { .b6x16_p32 , .b4x16_p64 } .dst_fmt = { .b8x16 } .shape = { .128x256b, .4x256b, .128x128b, .64x128b**, .32x128b*** } .multicast = { .warpx2::02_13** , .warpx2::01_23**, .warpx4*** }

9.7.18.9.3. TensorCore 第五代指令：tcgen05.shift

.cta_group = { .cta_group::1, .cta_group::2 }

9.7.18.10. TensorCore 第五代矩阵乘加运算

9.7.18.10.1. 转置与取负运算

9.7.18.10.2. 矩阵布局组织

9.7.18.10.3. 类型大小、主序与重排的有效组合

9.7.18.10.4. Tensor 与共享内存中元素的打包格式

9.7.18.10.4.1. Tensor Memory 中矩阵 D 的打包格式

9.7.18.10.4.2. 矩阵 A 与 B 的打包格式

9.7.18.10.4.3. .kind::mxf8f6f4 在 Tensor Memory 中用于矩阵 A 的打包格式

9.7.18.10.4.4. .kind::mxf8f6f4 在共享内存中用于矩阵 A 与 B 的打包格式

9.7.18.10.4.5. .kind::mxf4 与 .kind::mxf4nvf4 在 Tensor Memory 中用于矩阵 A 的打包格式

9.7.18.10.4.6. .kind::mxf4 与 .kind::mxf4nvf4 在共享内存中用于矩阵 A 与 B 的打包格式

9.7.18.10.5. 数据通路布局组织

9.7.18.10.5.1. 布局 A（M = 256）

9.7.18.10.5.2. 布局 B（M = 128 + cta_group::2 + 稠密 A 矩阵）

9.7.18.10.5.3. 布局 C（M = 128 + cta_group::2 + 稀疏 A 矩阵）

9.7.18.10.5.4. 布局 D（M = 128 + cta_group::1）

9.7.18.10.5.5. 布局 E（M = 64 + .ws 模式）

9.7.18.10.5.6. 布局 F（M = 64 + 非 .ws 模式）

9.7.18.10.5.7. 布局 G（M = 32）

9.7.18.10.6. 共享内存布局与重排

9.7.18.10.7. tcgen05.mma 的块缩放

9.7.18.10.7.1. scale_vectorsize 与类型、MMA-Kind 的有效组合

9.7.18.10.7.2. 缩放因子 A ID

9.7.18.10.7.2.1. scale_vec::1X/block32 且 K=32/K=64 时缩放因子 A 矩阵的布局

9.7.18.10.7.2.2. scale_vec::2X/block32 且 K=64/K=128 时缩放因子 A 矩阵的布局

9.7.18.10.7.2.3. scale_vec::4X/block16 且 K=64/K=128 时缩放因子 A 矩阵的布局

9.7.18.10.7.2.4. block32 且 K=96 时缩放因子 A 矩阵的布局（语义上等价于 scale_vec::3X）

9.7.18.10.7.2.5. block16 且 K=96 时缩放因子 A 矩阵的布局（语义上等价于 scale_vec::6X）

9.7.18.10.7.2.6. block16 且 K=128/256 时缩放因子 A 矩阵的布局（语义上等价于 scale_vec::8X）

9.7.18.10.7.3. 缩放因子 B ID

9.7.18.10.7.3.1. scale_vec::1X/block32 且 K=32/K=64 时缩放因子 B 矩阵的布局

9.7.18.10.7.3.2. scale_vec::2X/block32 且 K=64/K=128 时缩放因子 B 矩阵的布局

9.7.18.10.7.3.3. scale_vec::4X/block16 且 K=64/K=128 时缩放因子 B 矩阵的布局

9.7.18.10.7.3.4. block32 且 K=96 时缩放因子 B 矩阵的布局（语义上等价于 scale_vec::3X）

9.7.18.10.7.3.5. block16 且 K=96 的缩放因子 B 矩阵布局（语义等价于 scale_vec::6X）

9.7.18.10.7.3.6. block16 且 K=128/256 的缩放因子 B 矩阵布局（语义等价于 scale_vec::8X）

9.7.18.10.8. 输入矩阵的解压缩

9.7.18.10.9. 稀疏矩阵

9.7.18.10.9.1. 带 .kind::tf32 的稀疏 tcgen05.mma.sp

9.7.18.10.9.2. 带 .kind::f16、.kind::f8f6f4、.kind::mxf8f6f4、.kind::i8、.kind::ti16 的稀疏 tcgen05.mma.sp

9.7.18.10.9.3. 带 .kind::mxf4 和 .kind::mxf4nvf4 的稀疏 tcgen05.mma.sp

9.7.18.10.9.4. 稀疏性选择器

9.7.18.10.9.4.1. M = 64 时 .kind::f16、.kind::ti16 的稀疏元数据矩阵布局

9.7.18.10.9.4.2. M = 128 / M = 256 时 .kind::f16、.kind::ti16 的稀疏元数据矩阵布局

9.7.18.10.9.4.3. M = 64 时 .kind::tf32 的稀疏元数据矩阵布局

9.7.18.10.9.4.4. M = 128 / M = 256 时 .kind::tf32 的稀疏元数据矩阵布局

9.7.18.10.9.4.5. M = 64 时 .kind::f8f6f4、.kind::mxf8f6f4、.kind::i8、.kind::mxf4、.kind::mxf4nvf4 的稀疏元数据矩阵布局

9.7.18.10.9.4.6. M = 128 / M = 256 时 .kind::f8f6f4、.kind::mxf8f6f4、.kind::i8、.kind::mxf4、.kind::mxf4nvf4 的稀疏元数据矩阵布局

9.7.18.10.9.5. 对齐限制

9.7.18.10.10. TensorCore 第五代 MMA 指令

9.7.18.10.10.1. TensorCore 第五代指令：tcgen05.mma

tcgen05.mma.cta_group.kind [d-tmem], a-desc, b-desc, idesc, { disable-output-lane }, enable-input-d {, scale-input-d};

tcgen05.mma.cta_group.kind [d-tmem], [a-tmem], b-desc, idesc, { disable-output-lane }, enable-input-d {, scale-input-d};

.kind = { .kind::f16, .kind::tf32, .kind::f8f6f4 } .cta_group = { .cta_group::1, .cta_group::2 }

// 2. Floating-point type with block scaling:

tcgen05.mma.cta_group.kind.block_scale{.scale_vectorsize} [d-tmem], a-desc, b-desc, idesc, [scale-A-tmem], [scale-B-tmem], enable-input-d;

tcgen05.mma.cta_group.kind.block_scale{.scale_vectorsize} [d-tmem], [a-tmem], b-desc, idesc, [scale-A-tmem], [scale-B-tmem], enable-input-d;

.kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } .cta_group = { .cta_group::1, .cta_group::2 } .scale_vectorsize = { .scale_vec::1X, .scale_vec::2X, .scale_vec::4X, .block16, .block32 }

// 3. Convolution MMA for floating-point type without block scaling:

tcgen05.mma.cta_group.kind.collector_a_usage{.collector_b_usage} [d-tmem], a-desc, b-desc, idesc, { disable-output-lane }, enable-input-d {, scale-input-d};

tcgen05.mma.cta_group.kind{.ashift}.collector_a_usage{.collector_b_usage} [d-tmem], [a-tmem], b-desc, idesc, { disable-output-lane }, enable-input-d {, scale-input-d};

tcgen05.mma.cta_group.kind.ashift{.collector_a_usage}{.collector_b_usage} [d-tmem], [a-tmem], b-desc, idesc, { disable-output-lane }, enable-input-d {, scale-input-d};

.kind = { .kind::f16, .kind::tf32, .kind::f8f6f4 } .cta_group = { .cta_group::1, .cta_group::2 } .collector_a_usage = { .collector::buffer_a::op } .collector_b_usage = { .collector::buffer_b::op } ::buffer_a = { ::a } ::buffer_b = { ::b } ::op = { ::fill, ::use, ::lastuse, ::discard* }

// 4. Activation Stationary MMA for floating-point type with block scaling:

tcgen05.mma.cta_group.kind.block_scale{.scale_vectorsize}.collector_a_usage{.collector_b_usage} [d-tmem], a-desc, b-desc, idesc, [scale-A-tmem], [scale-B-tmem], enable-input-d;

tcgen05.mma.cta_group.kind.block_scale{.scale_vectorsize}.collector_a_usage{.collector_b_usage} [d-tmem], [a-tmem], b-desc, idesc, [scale-A-tmem], [scale-B-tmem], enable-input-d;

.cta_group = { .cta_group::1, .cta_group::2 } .scale_vectorsize = { .scale_vec::1X, .scale_vec::2X, .scale_vec::4X, .block16, .block32 } .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } .collector_a_usage = { .collector::buffer_a::op } .collector_b_usage = { .collector::buffer_b::op } ::buffer_a = { ::a } ::buffer_b = { ::b } ::op = { ::fill, ::use, ::lastuse, ::discard* }

// 5. Integer type:

tcgen05.mma.cta_group.kind [d-tmem], a-desc, b-desc, idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.cta_group.kind [d-tmem], [a-tmem], b-desc, idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.cta_group.kind::ti16.collector_b_usage [d-tmem], a-desc, b-desc, idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.cta_group.kind::ti16.collector_b_usage [d-tmem], [a-tmem], b-desc, idesc, { disable-output-lane }, enable-input-d;

.cta_group = { .cta_group::1, .cta_group::2 } .kind = { .kind::i8, .kind::ti16 } .collector_b_usage = { .collector::buffer::op } ::buffer = { ::b } ::op = { ::fill, ::use, ::lastuse, ::discard* }

// 6. Convolution MMA for integer type:

tcgen05.mma.cta_group.kind.collector_a_usage [d-tmem], a-desc, b-desc, idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.cta_group.kind.ashift{.collector_a_usage} [d-tmem], [a-tmem], b-desc, idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.cta_group.kind{.ashift}.collector_a_usage [d-tmem], [a-tmem], b-desc, idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.cta_group.kind::ti16.collector_a_usage.collector_b_usage [d-tmem], a-desc, b-desc, idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.cta_group.kind::ti16.ashift{.collector_a_usage}.collector_b_usage [d-tmem], [a-tmem], b-desc, idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.cta_group.kind::ti16{.ashift}.collector_a_usage.collector_b_usage [d-tmem], [a-tmem], b-desc, idesc, { disable-output-lane }, enable-input-d;

.cta_group = { .cta_group::1, .cta_group::2 } .kind = { .kind::i8, .kind::ti16 } .collector_a_usage = { .collector::buffer_a::op } .collector_b_usage = { .collector::buffer_b::op } ::buffer_a = { ::a } ::buffer_b = { ::b } ::op = { ::fill, ::use, ::lastuse, ::discard* }

// 7. Decompression of pre-compressed B matrix

tcgen05.mma.cta_group.kind::f8f6f4.decompress::lut::b{.collector_a_usage}{.collector_b_usage} [d-tmem], a-desc, b-compressed-desc, [b-decompress-metadata], idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.cta_group.kind::f8f6f4.decompress::lut::b{.collector_a_usage}{.collector_b_usage} [d-tmem], [a-tmem], b-compressed-desc, [b-decompress-metadata], idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.cta_group.kind::mxf8f6f4.block_scale.decompress::lut::b{.scale_vectorsize}{.collector_a_usage}{.collector_b_usage} [d-tmem], a-desc, b-compressed-desc, [b-decompress-metadata], idesc, [scale-A-tmem], [scale-B-tmem], enable-input-d;

tcgen05.mma.cta_group.kind::mxf8f6f4.block_scale.decompress::lut::b{.scale_vectorsize}{.collector_a_usage}{.collector_b_usage} [d-tmem], [a-tmem], b-compressed-desc, [b-decompress-metadata], idesc, [scale-A-tmem], [scale-B-tmem], enable-input-d;

.cta_group = { .cta_group::1, .cta_group::2 } .scale_vectorsize = { .block32 } .collector_a_usage = { .collector::buffer_a::op } .collector_b_usage = { .collector::buffer_b::op } ::buffer_a = { ::a } ::buffer_b = { ::b } ::op = { ::fill, ::use, ::lastuse, ::discard* }

tcgen05.commit.cta_group::1.mbarrier::arrive::one.b64 [mbarObj0];

loop: mbarrier.try_wait.parity.b64 p, [mbarObj0], 0; @!p bra loop;

9.7.18.10.10.2. TensorCore 第五代指令：tcgen05.mma.sp

tcgen05.mma.sp.cta_group.kind [d-tmem], a-desc, b-desc, [sp-meta-tmem] , idesc, { disable-output-lane }, enable-input-d{, scale-input-d};

tcgen05.mma.sp.cta_group.kind [d-tmem], [a-tmem], b-desc, [sp-meta-tmem] , idesc, { disable-output-lane }, enable-input-d{, scale-input-d};

.kind = { .kind::f16, , .kind::tf32, .kind::f8f6f4 } .cta_group = { .cta_group::1, .cta_group::2 }

// 2. Floating-point type with block scaling:

tcgen05.mma.sp.cta_group.kind.block_scale{.scale_vectorsize} [d-tmem], a-desc, b-desc , [sp-meta-tmem] , idesc, [scale-A-tmem], [scale-B-tmem], enable-input-d;

tcgen05.mma.sp.cta_group.kind.block_scale{.scale_vectorsize} [d-tmem], [a-tmem], b-desc , [sp-meta-tmem] , idesc, [scale-A-tmem], [scale-B-tmem], enable-input-d;

.scale_vectorsize = { .scale_vec::1X, .scale_vec::2X, .scale_vec::4X, .block16, .block32 } .cta_group = { .cta_group::1, .cta_group::2 } .kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 }

// 3. Convolution MMA with floating-point type without block scaling:

tcgen05.mma.sp.cta_group.kind.collector_a_usage{.collector_b_usage} [d-tmem], a-desc, b-desc, [sp-meta-tmem] , idesc, { disable-output-lane }, enable-input-d {, scale-input-d};

tcgen05.mma.sp.cta_group.kind.ashift{.collector_a_usage}{.collector_b_usage} [d-tmem], [a-tmem], b-desc, [sp-meta-tmem] , idesc, { disable-output-lane }, enable-input-d {, scale-input-d};

tcgen05.mma.sp.cta_group.kind{.ashift}.collector_a_usage{.collector_b_usage} [d-tmem], [a-tmem], b-desc, [sp-meta-tmem] , idesc, { disable-output-lane }, enable-input-d {, scale-input-d};

.kind = { .kind::f16, .kind::tf32, .kind::f8f6f4 } .collector_a_usage = { .collector::buffer_a::op } .collector_b_usage = { .collector::buffer_b::op } ::buffer_a = { ::a } ::buffer_b = { ::b } ::op = { ::fill, ::use, ::lastuse, ::discard* }

// 4. Activation Stationary MMA with floating-point type with block scaling:

tcgen05.mma.sp.cta_group.kind.block_scale{.scale_vectorsize}.collector_a_usage{.collector_b_usage} [d-tmem], a-desc, b-desc , [sp-meta-tmem] , idesc, [scale-A-tmem], [scale-B-tmem], enable-input-d;

tcgen05.mma.sp.cta_group.kind.block_scale{.scale_vectorsize}.collector_a_usage{.collector_b_usage} [d-tmem], [a-tmem], b-desc , [sp-meta-tmem] , idesc, [scale-A-tmem], [scale-B-tmem], enable-input-d;

.kind = { .kind::mxf8f6f4, .kind::mxf4, .kind::mxf4nvf4 } .scale_vectorsize = { .scale_vec::1X, .scale_vec::2X, .scale_vec::4X, .block16, .block32 } .collector_a_usage = { .collector::buffer_a::op } .collector_b_usage = { .collector::buffer_b::op } ::buffer_a = { ::a } ::buffer_b = { ::b } ::op = { ::fill, ::use, ::lastuse, ::discard* }

// 5. Integer type:

tcgen05.mma.sp.cta_group.kind [d-tmem], a-desc, b-desc, [sp-meta-tmem] , idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.sp.cta_group.kind [d-tmem], [a-tmem], b-desc, [sp-meta-tmem] , idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.sp.cta_group.kind::ti16.collector_b_usage [d-tmem], a-desc, b-desc, idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.sp.cta_group.kind::ti16.collector_b_usage [d-tmem], [a-tmem], b-desc, idesc, { disable-output-lane }, enable-input-d;

.cta_group = { .cta_group::1, .cta_group::2 } .kind = { .kind::i8, .kind::ti16 } .collector_b_usage = { .collector::buffer::op } ::buffer = { ::b } ::op = { ::fill, ::use, ::lastuse, ::discard* }

// 6. Convolution MMA with Integer type:

tcgen05.mma.sp.cta_group.kind.collector_a_usage [d-tmem], a-desc, b-desc, [sp-meta-tmem] , idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.sp.cta_group.kind.ashift{.collector_a_usage} [d-tmem], [a-tmem], b-desc, [sp-meta-tmem], idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.sp.cta_group.kind{.ashift}.collector_a_usage [d-tmem], [a-tmem], b-desc, [sp-meta-tmem], idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.sp.cta_group.kind::ti16.collector_a_usage.collector_b_usage [d-tmem], a-desc, b-desc, idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.sp.cta_group.kind::ti16.ashift{.collector_a_usage}.collector_b_usage [d-tmem], [a-tmem], b-desc, idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.sp.cta_group.kind::ti16{.ashift}.collector_a_usage.collector_b_usage [d-tmem], [a-tmem], b-desc, idesc, { disable-output-lane }, enable-input-d;

tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.collector::a:fill [taddr2], [taddr1], bdesc, [tmem_spmeta1], idesc, [tmem_scaleA], [tmem_scaleB], p;

tcgen05.commit.cta_group::1.mbarrier::arrive::one.b64 [mbarObj0];

loop: mbarrier.try_wait.parity.b64 p, [mbarObj0], 0; @!p bra loop;

9.7.18.10.10.3. TensorCore 第五代指令：tcgen05.mma.ws

tcgen05.mma.ws.cta_group::1.kind{.collector_usage} [d-tmem], a-desc, b-desc, idesc, enable-input-d {, zero-column-mask-desc };

tcgen05.mma.ws.cta_group::1.kind{.collector_usage} [d-tmem], [a-tmem], b-desc, idesc, enable-input-d {, zero-column-mask-desc };

.kind = { .kind::f16, .kind::tf32, .kind::f8f6f4 }

// 2. Integer type:

tcgen05.mma.ws.cta_group::1.kind{.collector_usage} [d-tmem], a-desc, b-desc, idesc, enable-input-d {, zero-column-mask-desc};

tcgen05.mma.ws.cta_group::1.kind{.collector_usage} [d-tmem], [a-tmem], b-desc, idesc, enable-input-d {, zero-column-mask-desc};

.collector_usage = { .collector::buffer::op } .kind = { .kind::i8, .kind::ti16 } ::buffer = { ::b0, ::b1, ::b2, ::b3 } ::op = { ::fill, ::use, ::lastuse, ::discard}

loop: mbarrier.try_wait.parity.b64 p, [mbarObj0], 0; @!p bra loop;

9.7.18.10.10.4. TensorCore 第五代指令：tcgen05.mma.ws.sp

tcgen05.mma.ws.sp.cta_group::1.kind{.collector_usage} [d-tmem], a-desc, b-desc, [sp-meta-tmem] , idesc, enable-input-d {, zero-column-mask-desc};

tcgen05.mma.ws.sp.cta_group::1.kind{.collector_usage} [d-tmem], [a-tmem], b-desc, [sp-meta-tmem] , idesc, enable-input-d {, zero-column-mask-desc};

.kind = { .kind::f16, .kind::tf32, .kind::f8f6f4 }

// 2. Integer type:

tcgen05.mma.ws.sp.cta_group::1.kind{.collector_usage} [d-tmem], a-desc, b-desc, [sp-meta-tmem] , idesc, enable-input-d {, zero-column-mask-desc};

tcgen05.mma.ws.sp.cta_group::1.kind{.collector_usage} [d-tmem], [a-tmem], b-desc, [sp-meta-tmem] , idesc, enable-input-d {, zero-column-mask-desc};

.collector_usage = { .collector::buffer::op } .kind = { .kind::i8, .kind::ti16 } ::buffer = { ::b0, ::b1, ::b2, ::b3 } ::op = { ::fill, ::use, ::lastuse, ::discard }

tcgen05.commit.cta_group::1.mbarrier::arrive::one.b64 [mbarObj0];

loop: mbarrier.try_wait.parity.b64 p, [mbarObj0], 0; @!p bra loop;

9.7.18.11. TensorCore 第五代专用同步操作

9.7.18.11.1. TensorCore 第五代指令：tcgen05.fence

tcgen05.cp.cta_group::1.128x256b [taddr0], sdesc0;

tcgen05.fence::before_thread_sync; st.relaxed.b32 [flag], 1;

// Consumer thread:

loop: ld.relaxed.b32 r, [flag]; setp.eq.u32 p, r, 1; @!p bra loop;

tcgen05.fence::after_thread_sync; tcgen05.mma.cta_group.kind [taddr0], adesc, bdesc, idesc, p;

9.7.18.12. TensorCore 第五代异步同步操作

9.7.18.12.1. TensorCore 第五代指令：tcgen05.commit

tcgen05.commit.cta_group.completion_mechanism.sync_restrict::shared::read::mma::a{.shared::cluster}{.multicast}.b64 [mbar] {, ctaMask};

.completion_mechanism = { .mbarrier::arrive::one } .cta_group = { .cta_group::1, .cta_group::2 } .multicast = { .multicast::cluster{::16b, ::32b} }

loop: mbarrier.try_wait.parity.b64 p, [mbarObj1], 0; @!p bra loop;

Example 2: tcgen05.mma.cta_group::2.kind::tf32 [taddr0], adesc, bdesc, idesc, p; tcgen05.commit.shared::cluster.multicast::cluster::32b.cta_group::2.mbarrier::arrive::one.b64 [mbarObj2];

loop: mbarrier.try_wait.parity.b64 p, [mbarObj2], 0; @!p bra loop;

// Example 3: tcgen05.mma.cta_group::2.kind::tf32 [taddr0], adesc, bdesc, idesc, p; tcgen05.mma.cta_group::2.kind::tf32 [taddr1], adesc1, bdesc1, idesc1, p1; tcgen05.commit.cta_group::2.mbarrier::arrive::one.sync_restrict::shared::read::mma::a.b64 [mbarObj2];

9.7.19. 栈操作指令

9.7.19.1. 栈操作指令：stacksave

.type = { .u32, .u64 };

.reg .u64 rd1; stacksave.u64 rd1;

9.7.19.2. 栈操作指令：stackrestore

.type = { .u32, .u64 };

9.7.19.3. 栈操作指令：alloca

.type = { .u32, .u64 };

a = max(immAlign, frame_align); // frame_align is the minimum guaranteed alignment

// Allocate size bytes of stack memory with alignment a and update the stack pointer. // Since the stack grows down, the updated stack pointer contains a lower address. stackptr = alloc_stack_mem(size, a);

// Return the new value of stack pointer as ptr. Since ptr is the lowest address of the memory // allocated by alloca, the memory can be accessed using ptr up to (ptr + size of allocated memory). stacksave ptr;

stacksave.u32 stackptr; // Save the current stack pointer alloca ptr, size, 8; // Allocate stack memory st.local.u32 [ptr], ra; // Use the allocated stack memory stackrestore.u32 stackptr; // Deallocate memory by restoring the stack pointer

9.7.20. 视频指令

9.7.20.1. 标量视频指令

// 32-bit scalar operation, with optional data merge vop.dtype.atype.btype{.sat} d.dsel, a{.asel}, b{.bsel}, c;

.dtype = .atype = .btype = { .u32, .s32 }; .dsel = .asel = .bsel = { .b0, .b1, .b2, .b3, .h0, .h1 }; .secop = { .add, .min, .max };

switch ( dsel ) {
    case .b0, .b1, .b2, .b3:
        if ( sign )  return CLAMP( tmp, S8_MAX, S8_MIN );
        else         return CLAMP( tmp, U8_MAX, U8_MIN );
    case .h0, .h1:
        if ( sign )  return CLAMP( tmp, S16_MAX, S16_MIN );
        else         return CLAMP( tmp, U16_MAX, U16_MIN );
    default:
        if ( sign )  return CLAMP( tmp, S32_MAX, S32_MIN );
        else         return CLAMP( tmp, U32_MAX, U32_MIN );
}

}

9.7.20.1.1. 标量视频指令：vadd , vsub , vabsdiff , vmin , vmax

// 32-bit scalar operation, with optional data merge vop.dtype.atype.btype{.sat} d.dsel, a{.asel}, b{.bsel}, c;

vop = { vadd, vsub, vabsdiff, vmin, vmax }; .dtype = .atype = .btype = { .u32, .s32 }; .dsel = .asel = .bsel = { .b0, .b1, .b2, .b3, .h0, .h1 }; .op2 = { .add, .min, .max };

switch ( vop ) { case vadd: tmp = ta + tb; case vsub: tmp = ta - tb; case vabsdiff: tmp = | ta - tb |; case vmin: tmp = MIN( ta, tb ); case vmax: tmp = MAX( ta, tb ); } // saturate, taking into account destination type and merge operations tmp = optSaturate( tmp, sat, isSigned(dtype), dsel ); d = optSecondaryOp( op2, tmp, c ); // optional secondary operation d = optMerge( dsel, tmp, c ); // optional merge with c operand

9.7.20.1.2. 标量视频指令：vshl , vshr

// 32-bit scalar operation, with optional data merge vop.dtype.atype.u32{.sat}.mode d.dsel, a{.asel}, b{.bsel}, c;

vop = { vshl, vshr }; .dtype = .atype = { .u32, .s32 }; .mode = { .clamp, .wrap }; .dsel = .asel = .bsel = { .b0, .b1, .b2, .b3, .h0, .h1 }; .op2 = { .add, .min, .max };

9.7.20.1.3. 标量视频指令：vmad

.dtype = .atype = .btype = { .u32, .s32 }; .asel = .bsel = { .b0, .b1, .b2, .b3, .h0, .h1 }; .scale = { .shr7, .shr15 };

lsb = 0; if ( .po ) { lsb = 1; } else if ( a.negate ^ b.negate ) { tmp = ~tmp; lsb = 1; } else if ( c.negate ) { c = ~c; lsb = 1; }

c128[127:0] = (signedFinal) sext32( c ) : zext ( c ); tmp = tmp + c128 + lsb; switch( scale ) { case .shr7: result = (tmp >> 7) & 0xffffffffffffffff; case .shr15: result = (tmp >> 15) & 0xffffffffffffffff; } if ( .sat ) { if (signedFinal) result = CLAMP(result, S32_MAX, S32_MIN); else result = CLAMP(result, U32_MAX, U32_MIN); }

9.7.20.1.4. 标量视频指令：vset

// 32-bit scalar operation, with optional data merge vset.atype.btype.cmp d.dsel, a{.asel}, b{.bsel}, c;

.atype = .btype = { .u32, .s32 }; .cmp = { .eq, .ne, .lt, .le, .gt, .ge }; .dsel = .asel = .bsel = { .b0, .b1, .b2, .b3, .h0, .h1 }; .op2 = { .add, .min, .max };

9.7.20.2. SIMD 视频指令

.dtype = .atype = .btype = { .u32, .s32 }; .mask = { .h0, .h1, .h10 }; .asel = .bsel = { .hxy, where x,y are from { 0, 1, 2, 3 } };

.dtype = .atype = .btype = { .u32, .s32 }; .mask = { .b0, .b1, .b10 .b2, .b20, .b21, .b210, .b3, .b30, .b31, .b310, .b32, .b320, .b321, .b3210 }; .asel = .bsel = .bxyzw, where x,y,z,w are from { 0, ..., 7 };

9.7.20.2.1. SIMD 视频指令：vadd2 , vsub2 , vavrg2 , vabsdiff2 , vmin2 , vmax2

// SIMD instruction with secondary accumulate operation vop2.dtype.atype.btype.add d{.mask}, a{.asel}, b{.bsel}, c;

vop2 = { vadd2, vsub2, vavrg2, vabsdiff2, vmin2, vmax2 }; .dtype = .atype = .btype = { .u32, .s32 }; .mask = { .h0, .h1, .h10 }; // defaults to .h10 .asel = .bsel = { .hxy, where x,y are from { 0, 1, 2, 3 } }; .asel defaults to .h10 .bsel defaults to .h32

for (i=0; i<2; i++) { switch ( vop2 ) { case vadd2: t[i] = Va[i] + Vb[i]; case vsub2: t[i] = Va[i] - Vb[i]; case vavrg2: if ( ( Va[i] + Vb[i] ) >= 0 ) { t[i] = ( Va[i] + Vb[i] + 1 ) >> 1; } else { t[i] = ( Va[i] + Vb[i] ) >> 1; } case vabsdiff2: t[i] = | Va[i] - Vb[i] |; case vmin2: t[i] = MIN( Va[i], Vb[i] ); case vmax2: t[i] = MAX( Va[i], Vb[i] ); } if (.sat) { if ( .dtype == .s32 ) t[i] = CLAMP( t[i], S16_MAX, S16_MIN ); else t[i] = CLAMP( t[i], U16_MAX, U16_MIN ); } } // secondary accumulate or SIMD merge mask = extractMaskBits( .mask ); if (.add) { d = c; for (i=0; i<2; i++) { d += mask[i] ? t[i] : 0; } } else { d = 0; for (i=0; i<2; i++) { d |= mask[i] ? t[i] : Vc[i]; } }

9.7.20.2.2. SIMD 视频指令：vset2

// SIMD instruction with secondary accumulate operation vset2.atype.btype.cmp.add d{.mask}, a{.asel}, b{.bsel}, c;

.atype = .btype = { .u32, .s32 }; .cmp = { .eq, .ne, .lt, .le, .gt, .ge }; .mask = { .h0, .h1, .h10 }; // defaults to .h10 .asel = .bsel = { .hxy, where x,y are from { 0, 1, 2, 3 } }; .asel defaults to .h10 .bsel defaults to .h32

9.7.20.2.3. SIMD 视频指令：vadd4、vsub4、vavrg4、vabsdiff4、vmin4、vmax4

// SIMD instruction with secondary accumulate operation vop4.dtype.atype.btype.add d{.mask}, a{.asel}, b{.bsel}, c; vop4 = { vadd4, vsub4, vavrg4, vabsdiff4, vmin4, vmax4 };

.dtype = .atype = .btype = { .u32, .s32 }; .mask = { .b0, .b1, .b10 .b2, .b20, .b21, .b210, .b3, .b30, .b31, .b310, .b32, .b320, .b321, .b3210 }; defaults to .b3210 .asel = .bsel = .bxyzw, where x,y,z,w are from { 0, ..., 7 }; .asel defaults to .b3210 .bsel defaults to .b7654

9.7.20.2.4. SIMD 视频指令：vset4

// SIMD instruction with secondary accumulate operation vset4.atype.btype.cmp.add d{.mask}, a{.asel}, b{.bsel}, c;

.atype = .btype = { .u32, .s32 }; .cmp = { .eq, .ne, .lt, .le, .gt, .ge }; .mask = { .b0, .b1, .b10 .b2, .b20, .b21, .b210, .b3, .b30, .b31, .b310, .b32, .b320, .b321, .b3210 }; defaults to .b3210 .asel = .bsel = .bxyzw, where x,y,z,w are from { 0, ..., 7 }; .asel defaults to .b3210 .bsel defaults to .b7654

9.7.21. 杂项指令

9.7.21.1. 杂项指令：brkpt

9.7.21.2. 杂项指令：nanosleep

nanosleep.u32 r; nanosleep.u32 42; @p nanosleep.u32 r;

9.7.21.3. 杂项指令：pmevent

9.7.21.4. 杂项指令：trap

9.7.21.5. 杂项指令：setmaxnreg

.action = { .inc, .dec };

PTX ISA 9.4：1. 简介

Thu, 24 Sep 2026 00:00:00 GMT

本文介绍 PTX：一种用于并行线程执行（Parallel Thread Execution）的低层次虚拟机及指令集架构（Instruction Set Architecture，ISA）。PTX 将 GPU 呈现为一个可进行数据并行计算的设备。

1.1. 利用 GPU 实现可扩展的数据并行计算

在市场对实时、高清 3D 图形的持续需求推动下，可编程 GPU 已发展为一种高度并行、支持多线程的众核处理器，拥有强大的计算能力和极高的内存带宽。GPU 尤其适合处理既能表达为数据并行计算、又具有较高算术强度（arithmetic intensity）的问题。数据并行计算是指在多个数据元素上并行执行同一个程序；这里的算术强度是指算术运算次数与内存操作次数之比。由于每个数据元素都执行相同的程序，对复杂流程控制的需求较低；同时，大量数据元素上的计算与较高的算术强度，使得内存访问延迟可以通过计算来隐藏，而不必依赖大型数据缓存。

数据并行处理将数据元素映射到并行执行的线程。许多处理大规模数据集的应用都可以采用数据并行编程模型来加速计算。在 3D 渲染中，大量像素和顶点被映射到并行线程。类似地，图像与媒体处理应用，例如渲染图像的后处理、视频编码与解码、图像缩放、立体视觉和模式识别，也可以将图像块与像素映射到并行处理线程。事实上，数据并行处理所加速的算法远不限于图像渲染和处理领域，还包括通用信号处理、物理仿真、计算金融和计算生物学等。

PTX 为通用并行线程执行定义了虚拟机和指令集架构。PTX 程序在安装时被转换为目标硬件的指令集。PTX 到 GPU 的转换器与驱动程序，使 NVIDIA GPU 能够作为可编程的并行计算机使用。

1.2. PTX 的设计目标

PTX 为通用并行编程提供稳定的编程模型和指令集。它旨在高效运行于支持 NVIDIA Tesla 架构所定义计算特性的 NVIDIA GPU。CUDA 和 C/C++ 等高级语言的编译器生成 PTX 指令，随后针对目标架构对这些指令进行优化，并将其转换为该架构的原生指令。

PTX 的设计目标包括：

提供跨越多代 GPU 的稳定指令集架构。
使编译后的应用程序获得与 GPU 原生代码相当的性能。
提供与具体机器无关的指令集架构，作为 C/C++ 等编译器的目标。
为应用程序和中间件开发者提供用于代码分发的指令集架构。
为优化型代码生成器和转换器提供通用的源代码级指令集架构，由这些工具将 PTX 映射到具体的目标机器。
便于手工编写库、高性能计算内核（kernel）和架构测试。
提供可扩展的编程模型，覆盖从单个计算单元到多个并行计算单元的不同 GPU 规模。

1.3. PTX ISA 9.4 版本

PTX ISA 9.4 版本引入了以下新特性：

新增对 sm_107 目标架构的支持。
新增对 sm_107f 目标的支持，该目标支持架构家族特定特性（family-specific features）。
新增对 sm_107a 目标的支持，该目标支持架构特定特性（architecture-specific features）。
为 set 指令新增 .u8x4、.s8x4、.u16x2、.s16x2 指令类型支持。
为 cvt 指令新增 .pzo 限定符支持。
当 cvt 指令的目标类型为 .e4m3x2、.e5m2x2、.e2m3x2、.e3m2x2、.e2m1x2 时，新增 .rz 舍入模式支持。
为 mbarrier.expect_tx、mbarrier.complete_tx、mbarrier.arrive、mbarrier.arrive_drop、cp.async.bulk、cp.async.bulk.tensor 和 tcgen05.commit 指令新增 .multicast::cluster::32b 限定符支持。
为 tcgen05.commit 指令新增 .sync_restrict::shared::read::mma::a 限定符支持。
为 cp.async.bulk.prefetch 和 cp.async.bulk.prefetch.tensor 指令新增 .level::eviction_priority 限定符支持。
新增 applypriority.async.bulk 和 applypriority.async.bulk.tensor 指令支持。
为 cp.async.bulk.tensor、cp.reduce.async.bulk.tensor、cp.async.bulk.prefetch.tensor 指令新增 .override::global_address 和 .override_attribute 限定符支持。
为 cp.async.bulk.tensor 和 cp.reduce.async.bulk.tensor 指令新增 .im2col_no_offs::w 限定符支持。
为 tcgen05.ld 和 tcgen05.ld.red 指令新增 .spcompress 限定符支持。
新增 spcompress 和 spdecompress 指令支持。
为 cvt 指令新增 .ue5m3x2 指令类型支持。
为 cvt 指令新增 .scaled::n1::ue8m0 限定符支持。
为 tcgen05.mma 和 tcgen05.mma.sp 指令新增 UE5M3 缩放因子类型。
为 tcgen05.mma、tcgen05.mma.sp、tcgen05.mma.ws、tcgen05.mma.ws.sp 指令新增 .kind::ti16 限定符支持。
新增 add、sub、mul 和 fma 指令对 .f16x2 / .bf16x2 / .f32x2 类型的支持。
新增 add、sub、mul 和 fma 指令对 FP8/FP6/FP4 x4 打包类型的支持。
为 tcgen05.alloc 和 tcgen05.dealloc 指令新增 .exclusive 限定符支持。
为 mbarrier.test_wait 和 mbarrier.try_wait 指令新增 .phase_type::* 限定符支持。
为 mbarrier.test_wait 和 mbarrier.try_wait 指令新增 reportPredicate 和 reportValue 操作数支持。
为 mbarrier 指令新增 .layout 限定符支持，并新增 mbarrier.check_layout 指令支持。
为 cp.async.bulk 和 cp.async.bulk.tensor 指令新增 .report_mechanism 限定符支持。
为 tcgen05.mma 指令新增 .decompress::lut::b 限定符支持。
为 tcgen05.mma 指令新增 .collector::b::* 限定符支持。
新增 .loc_intermediate 指示符和 .nv_intermediate_source_section 结构支持，用于中间表示（IR）的源代码位置映射。
为 prefetch 指令新增 .valid_addr 和 .L1::32B 限定符支持。
为 atom、red、cp.reduce.async.bulk 和 multimem.cp.reduce.async.bulk 指令新增 .f32 类型下的 .noftz 限定符支持。
为 ld 指令新增 .proxy::readonly 限定符支持。
新增 .minperctamemory 指示符，以及 %perctamemoryoffset、%perctamemorysize 特殊寄存器支持，用于每个 CTA（协作线程数组）的全局内存。
为 ldmatrix 指令新增 .m8n16 形状下的 .s8.s4 类型支持。
为 fence.proxy.async::generic 指令新增 .sync_restrict::shared::cluster::read 限定符支持。
为 fence.proxy 指令新增 .acquire、.release 限定符与 .alias 限定符配合使用的支持。
新增 fabric.try_get.async.tensor、fabric.try_put.async.tensor 和 fabric.try_red.async.tensor 指令支持。
新增 fabric.try_atom 指令支持。
新增 createpolicy.range.fabric 指令支持。
为 fabric.try_get、fabric.try_put 和 fabric.try_red 指令新增 .level::cache_hint 限定符支持。

1.4. 文档结构

本文档的信息按以下章节组织：

编程模型（Programming Model）：概述编程模型。
PTX 机器模型（PTX Machine Model）：概述 PTX 虚拟机模型。
语法（Syntax）：介绍 PTX 语言的基本语法。
状态空间、类型与变量（State Spaces, Types, and Variables）：介绍状态空间、类型和变量声明。
指令操作数（Instruction Operands）：介绍指令操作数。
ABI 抽象（Abstracting the ABI）：介绍函数与调用语法、调用约定，以及 PTX 对应用程序二进制接口（Application Binary Interface，ABI）抽象的支持。
指令集（Instruction Set）：介绍指令集。
特殊寄存器（Special Registers）：列出特殊寄存器。
汇编指示符（Directives）：列出 PTX 支持的汇编指示符。
版本说明（Release Notes）：提供 PTX ISA 2.x 及后续版本的发布说明。

754-2008 IEEE Standard for Floating-Point Arithmetic（IEEE 浮点算术标准）。ISBN 978-0-7381-5752-8，2008 年。
The OpenCL Specification（OpenCL 规范），版本 1.1，文档修订号 44，2011 年 6 月 1 日。
CUDA Programming Guide（CUDA 编程指南）。
CUDA Dynamic Parallelism Programming Guide（CUDA 动态并行编程指南）。
CUDA Atomicity Requirements（CUDA 原子性要求）。
PTX Writers Guide to Interoperability（PTX 编写者互操作性指南）。

PTX ISA 9.4

Wed, 23 Sep 2026 00:00:00 GMT

This series is adapted from the NVIDIA PTX ISA 9.4 documentation.

Chapters

PTX ISA 9.4: 1. Introduction

Wed, 23 Sep 2026 00:00:00 GMT

1.1. Scalable Data-Parallel Computing using GPUs

1.2. Goals of PTX

1.3. PTX ISA Version 9.4

1.4. Document Structure

PTX ISA 9.4: 2. Programming Model

Wed, 23 Sep 2026 00:00:00 GMT

2.1. A Highly Multithreaded Coprocessor

2.2. Thread Hierarchy

2.2.1. Cooperative Thread Arrays

2.2.2. Cluster of Cooperative Thread Arrays

2.2.3. Grid of Clusters

2.3. Memory Hierarchy

PTX ISA 9.4: 3. PTX Machine Model

Wed, 23 Sep 2026 00:00:00 GMT

3.1. A Set of SIMT Multiprocessors

3.2. Independent Thread Scheduling

3.3. On-chip Shared Memory

PTX ISA 9.4: 4. Syntax

Wed, 23 Sep 2026 00:00:00 GMT

4.1. Source Format

4.2. Comments

4.3. Statements

start: mov.b32 r1, %tid.x; shl.b32 r1, r1, 2; // shift thread id by 2 bits ld.global.b32 r2, array[r1]; // thread[tid] gets array[tid] add.f32 r2, r2, 0.5; // add 1/2

4.3.1. Directive Statements

4.3.2. Instruction Statements

4.4. Identifiers

4.5. Constants

4.5.1. Integer Constants

4.5.2. Floating-Point Constants

4.5.3. Predicate Constants

4.5.4. Constant Expressions

4.5.5. Integer Constant Expression Evaluation

4.5.6. Summary of Constant Expression Evaluation Rules

PTX ISA 9.4: 5. State Spaces, Types, and Variables

Wed, 23 Sep 2026 00:00:00 GMT

5.1. State Spaces

5.1.1. Register State Space

5.1.2. Special Register State Space

5.1.3. Constant State Space

5.1.3.1. Banked Constant State Space (deprecated)

5.1.4. Global State Space

5.1.5. Local State Space

5.1.6. Parameter State Space

5.1.6.1. Kernel Function Parameters

ld.param.u32 %n, [N];
ld.param.f64 %d, [buffer];
...

mov.u32      %ptr, len;
ld.param.u32 %n, [%ptr];
...

5.1.6.2. Kernel Function Parameter Attributes

5.1.6.3. Kernel Parameter Attribute: .ptr

.space = { .const, .global, .local, .shared };

5.1.6.4. Device Function Parameters

ld.param.f64 %d, [buffer];
ld.param.s32 %y, [buffer+8];
...

}

ld.param.u32 %n, [N];
mov.u32      %r, buffer;  // forces buffer to .local state space

Loop: setp.eq.u32 %p, %n, 0; @%p bra Done; ld.local.f32 %f, [%r]; ... add.u32 %r, %r, 4; sub.u32 %n, %n, 1; bra Loop; Done: ... }

5.1.7. Shared State Space

5.1.8. Texture State Space (deprecated)

5.2. Types

5.2.1. Fundamental Types

5.2.2. Restricted Use of Sub-Word Sizes

5.2.3. Alternate Floating-Point Data Formats

5.2.4. Fixed-point Data format

5.2.5. Packed Data Types

5.2.5.1. Packed Floating Point Data Types

5.2.5.2. Packed Integer Data Types

5.2.5.3. Packed Fixed-Point Data Types

5.3. Texture Sampler and Surface Types

5.3.1. Texture and Surface Properties

5.3.2. Sampler Properties

5.3.3. Channel Data Type and Channel Order Fields

5.4. Variables

5.4.1. Variable Declarations

5.4.2. Vectors

5.4.3. Array Declarations

5.4.4. Initializers

// array of generic-address pointers to elements of bar .global .u32 parr[] = { generic(bar), generic(bar)+4, generic(bar)+8 };

// examples using mask() operator are pruned for brevity .global .u8 addr[] = {0xff(foo), 0xff00(foo), 0xff0000(foo), ...};

.global .u8 addr2[] = {0xff(foo+4), 0xff00(foo+4), 0xff0000(foo+4),...}

.global .u8 addr3[] = {0xff(generic(foo)), 0xff00(generic(foo)),...}

.global .u8 addr4[] = {0xff(generic(foo)+4), 0xff00(generic(foo)+4),...}

// mask() operator with integer const expression .global .u8 addr5[] = { 0xFF(1000 + 546), 0xFF00(131187), ...};

.global .u32 foo[] = { 2, 3, 5, 7, 9, 11 }; .global .u64 ptr = generic(foo); // generic address of foo[0] .global .u64 ptr = generic(foo)+8; // generic address of foo[2]

5.4.5. Alignment

5.4.6. Parameterized Variable Names

5.4.7. Variable Attributes

5.4.8. Variable and Function Attribute Directive: .attribute

.global .attribute(.unified(19,95)) .f32 f;

.func .attribute(.unified(0xAB, 0xCD)) bar() { ... }

5.5. Tensors

5.5.1. Tensor Dimension, size and format

5.5.1.1. Sub-byte Types

5.5.1.1.1. Padding and alignment of the sub-byte types

5.5.2. Tensor Access Modes

5.5.3. Tiled Mode

5.5.3.1. Bounding Box

5.5.3.2. Traversal-Stride

5.5.3.3. Out of Boundary Access

5.5.3.4. .tile::scatter4 and .tile::gather4 modes

5.5.3.4.1. Bounding Box

5.5.4. im2col mode

5.5.4.1. Bounding Box

tensor coordinates = (7, 7, 4, 0) im2col offsets : (0, 0)

tensor coordinates = (7, 7, 4, 0) im2col offsets: (2, 2)

5.5.4.2. Traversal Stride

5.5.4.3. Out of Boundary Access

5.5.5. im2col::w , im2col_no_offs::w and im2col::w::128 modes

5.5.5.1. Bounding Box

5.5.5.2. Traversal Stride

5.5.5.3. wHalo

Tensor Coordinates in the instruction = (7, 2, 3, 0) wHalo in the instruction = 2 (as 3x3 convolution filter is used)

5.5.5.4. wOffset

Tensor Coordinates in the instruction = (7, 2, -1, 0)

Shared memory buffer 1: wHalo = 1 wOffset = 0

Shared memory buffer 2: wHalo = 0 wOffset = 1

Tensor Coordinates in the instruction = (7, 2, -1, 0)

Shared memory buffer 1: wHalo = 0 wOffset = 0

Shared memory buffer 2: wHalo = 0 wOffset = 1

Shared memory buffer 3: wHalo = 0 wOffset = 2

5.5.6. Interleave layout

5.5.7. Swizzling Modes

5.5.8. Tensor-map

PTX ISA 9.4: 6. Instruction Operands

Wed, 23 Sep 2026 00:00:00 GMT

6.1. Operand Type Information

6.2. Source Operands

6.3. Destination Operands

6.4. Using Addresses, Arrays, and Vectors

6.4.1. Addresses as Operands

ld.shared.u16 r0,[x]; ld.global.v4.f32 W, [V]; ld.const.s32 q, [tbl+12]; mov.u32 p, tbl;

6.4.1.1. Generic Addressing

6.4.2. Arrays as Operands

6.4.3. Vectors as Operands

mov.v4.f32 {a,b,c,d}, V;

6.4.4. Labels and Function Names as Operands

6.5. Type Conversion

6.5.1. Scalar Conversions

6.5.2. Rounding Modifiers

6.6. Operand Costs

PTX ISA 9.4: 7. Abstracting the ABI

Wed, 23 Sep 2026 00:00:00 GMT

7.1. Function Declarations and Definitions

...
call foo;
...

...
call (%r1), inc_ptr, (%r1,4);
...

7.1.1. Changes from PTX ISA Version 1.x

7.2. Variadic Functions

7.3. Alloca

PTX ISA 9.4: 8. Memory Consistency Model

Wed, 23 Sep 2026 00:00:00 GMT

8.1. Scope and applicability of the model

8.1.1. Limitations on atomicity at system scope

8.2. Memory operations

8.2.1. Overlap

8.2.2. Aliases

8.2.3. Multimem Addresses

8.2.4. Memory Operations on Vector Data Types

8.2.5. Memory Operations on Packed Data Types

8.2.6. Initialization

8.3. State spaces

8.4. Operation types

8.4.1. mmio Operation

8.4.2. volatile Operation

8.5. Scope

8.6. Proxies

8.6.1. Strong Proxy Accesses

8.7. Morally strong operations

8.7.1. Conflict and Data-races

8.7.2. Limitations on Mixed-size Data-races

8.8. Release and Acquire Patterns

8.9. Ordering of memory operations

8.9.1. Program Order

8.9.1.1. Asynchronous Operations

8.9.2. Observation Order

8.9.3. Fence-SC Order

8.9.4. Memory synchronization

8.9.5. Causality Order

8.9.6. Coherence Order

8.9.7. Communication Order

8.10. Axioms

8.10.1. Coherence

8.10.2. Fence-SC

8.10.3. Atomicity

8.10.4. No Thin Air

8.10.5. Sequential Consistency Per Location

8.10.6. Causality

8.11. Special Cases

8.11.1. Reductions do not form Acquire Patterns

PTX ISA 9.4: 9. Instruction Set

Wed, 23 Sep 2026 00:00:00 GMT

9.1. Format and Semantics of Instruction Descriptions

9.2. PTX Instructions

9.3. Predicated Execution

9.3.1. Comparisons

9.3.1.1. Integer and Bit-Size Comparisons

9.3.1.2. Floating Point Comparisons

9.3.2. Manipulating Predicates

9.4. Type Information for Instructions and Operands

add.u16 d, a, b; // perform a 16-bit unsigned add

cvt.f32.u16 d, a; // convert 16-bit unsigned to 32-bit float

9.4.1. Operand Size Exceeding Instruction-Type Size

9.5. Divergence of Threads in Control Constructs

9.6. Semantics

9.6.1. Machine-Specific Semantics of 16-bit Code

9.7. Instructions

9.7.1. Integer Arithmetic Instructions

9.7.1.1. Integer Arithmetic Instructions: add

.type1 = { .u16, .u64, .s16, .s64 };

.type2 = { .u32, .u16x2, .u8x4, .s32, .s16x2, .s8x4 };

9.7.1.2. Integer Arithmetic Instructions: sub

.type1 = { .u16, .u32, .u64, .s16, .s64 };

.type2 = { .s32, .u8x4, .s8x4 };

9.7.1.3. Integer Arithmetic Instructions: mul

.mode = { .hi, .lo, .wide }; .type = { .u16, .u32, .u64, .s16, .s32, .s64 };

9.7.1.4. Integer Arithmetic Instructions: mad

.mode = { .hi, .lo, .wide }; .type = { .u16, .u32, .u64, .s16, .s32, .s64 };

9.7.1.5. Integer Arithmetic Instructions: clmad

.mode = { .hi, .lo };

for (i = 0; i < 64; i++) { if ((a & (1 << i)) != 0) { tmp ^= b << i; } }

// Select upper or lower 64 bits depending on the value of .mode. if (.mode == .lo) { d = tmp[63..0]; } else { d = tmp[127..64]; }

d ^= c; // carryless accumulation.

// Carryless multiply-add producing lower 64 bits of result. clmad.lo.u64 Rd, Ra, Rb, Rc;

// Carryless multiply-add producing higher 64 bits of result. clmad.hi.u64 Rd, Ra, Rb, Rc;

9.7.1.6. Integer Arithmetic Instructions: mul24

.mode = { .hi, .lo }; .type = { .u32, .s32 };

9.7.1.7. Integer Arithmetic Instructions: mad24

.mode = { .hi, .lo }; .type = { .u32, .s32 };

9.7.1.8. Integer Arithmetic Instructions: sad

.type = { .u16, .u32, .u64, .s16, .s32, .s64 };

9.7.1.9. Integer Arithmetic Instructions: div

.type = { .u16, .u32, .u64, .s16, .s32, .s64 };

9.7.1.10. Integer Arithmetic Instructions: rem

.type = { .u16, .u32, .u64, .s16, .s32, .s64 };

9.7.1.11. Integer Arithmetic Instructions: abs

.type = { .s16, .s32, .s64 };

9.7.1.12. Integer Arithmetic Instructions: neg

.type = { .s8x4, .s16, .s32, .s64 };

9.7.1.13. Integer Arithmetic Instructions: min

.type1 = { .u16, .u32, .u64, .u16x2, .u8x4, .s16, .s64 }; .type2 = { .s16x2, .s32, .s8x4 };

9.7.1.14. Integer Arithmetic Instructions: max

.type1 = { .u16, .u32, .u64, .u16x2, .u8x4, .s16, .s64 }; .type2 = { .s16x2, .s32, .s8x4 };

9.7.1.15. Integer Arithmetic Instructions: popc

.type = { .b32, .b64 };

9.7.1.16. Integer Arithmetic Instructions: clz

.type = { .b32, .b64 };

while (d < max && (a&mask == 0) ) { d++; a = a << 1; }

9.7.1.17. Integer Arithmetic Instructions: bfind

.type = { .u32, .u64, .s32, .s64 };

9.7.1.18. Integer Arithmetic Instructions: fns

while ((pos &gt;= 0) &amp;&amp; (pos &lt; 32)) {
    if (mask[pos] == 1) {
        if (count == 0) {
          d = pos;
          break;
       } else {
           count = count - 1;
       }
    }
    pos = pos + inc;
}

}

9.7.1.19. Integer Arithmetic Instructions: brev

.type = { .b32, .b64 };

for (i=0; i<=msb; i++) { d[i] = a[msb-i]; }

9.7.1.20. Integer Arithmetic Instructions: bfe

.type = { .u32, .u64, .s32, .s64 };

if (.type==.u32 || .type==.u64 || len==0) sbit = 0; else sbit = a[min(pos+len-1,msb)];

d = 0; for (i=0; i<=msb; i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit; }

9.7.1.21. Integer Arithmetic Instructions: bfi

.type = { .b32, .b64 };

f = b; for (i=0; i<len && pos+i<=msb; i++) { f[pos+i] = a[i]; }

9.7.1.22. Integer Arithmetic Instructions: szext

.mode = { .clamp, .wrap }; .type = { .u32, .s32 };

if (b1 == 0 || too_large || .type != .s32) { sign_bit = false; } else { sign_bit = (a >> sign_pos) & 1; } d = (a & ~mask) | (sign_bit ? mask | 0);

9.7.1.23. Integer Arithmetic Instructions: bmsk

.mode = { .clamp, .wrap };

sum-overflow = sum >= 32 ? true : false; bit-position-overflow = false; bit-width-overflow = false;

if (.mode == .clamp) { if (a >= 32) { bit-position-overflow = true; mask0 = 0; } if (b >= 32) { bit-width-overflow = true; } }

if (sum-overflow || bit-position-overflow || bit-width-overflow) { mask1 = 0; } else if (b1 == 0) { mask1 = ~0; } d = mask0 & ~mask1;

9.7.1.24. Integer Arithmetic Instructions: dp4a

.atype = .btype = { .u32, .s32 };

// Extract 4 bytes from a 32bit input and sign or zero extend // based on input type. Va = extractAndSignOrZeroExt_4(a, .atype); Vb = extractAndSignOrZeroExt_4(b, .btype);

for (i = 0; i < 4; ++i) { d += Va[i] * Vb[i]; }

9.7.1.25. Integer Arithmetic Instructions: dp2a

.atype = .btype = { .u32, .s32 }; .mode = { .lo, .hi };

// Extract four 8-bit values from a 32-bit input and sign or zer extend // based on input type. Vb = extractAndSignOrZeroExt_4(b, .btype);

b_select = (.mode == .lo) ? 0 : 2;

for (i = 0; i < 2; ++i) { d += Va[i] * Vb[b_select + i]; }

9.7.2. Extended-Precision Integer Arithmetic Instructions

9.7.2.1. Extended-Precision Arithmetic Instructions: add.cc

.type = { .u32, .s32, .u64, .s64 };

9.7.2.2. Extended-Precision Arithmetic Instructions: addc

.type = { .u32, .s32, .u64, .s64 };

9.7.2.3. Extended-Precision Arithmetic Instructions: sub.cc

.type = { .u32, .s32, .u64, .s64 };

9.7.2.4. Extended-Precision Arithmetic Instructions: subc

.type = { .u32, .s32, .u64, .s64 };

9.7.2.5. Extended-Precision Arithmetic Instructions: mad.cc

.type = { .u32, .s32, .u64, .s64 };

9.7.2.6. Extended-Precision Arithmetic Instructions: madc

.type = { .u32, .s32, .u64, .s64 };

9.7.3. Floating-Point Instructions

9.7.3.1. Floating Point Instructions: testp

.op = { .finite, .infinite, .number, .notanumber, .normal, .subnormal }; .type = { .f32, .f64 };

9.7.3.2. Floating Point Instructions: copysign

.type = { .f32, .f64 };

9.7.3.3. Floating Point Instructions: add

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.4. Floating Point Instructions: sub

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.5. Floating Point Instructions: mul

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.6. Floating Point Instructions: fma

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.7. Floating Point Instructions: mad

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.8. Floating Point Instructions: div

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.9. Floating Point Instructions: abs

9.7.3.10. Floating Point Instructions: neg

9.7.3.11. Floating Point Instructions: min

def min_nan (z, x, y) { if (isNaN(x) || isNaN(y)) z = NaN; else // note: -0.0 < +0.0 here z = (x < y) ? x : y; return z; }

def two_inputs_min (z, x, y) { if (.NaN) z = min_nan(z, x, y); else z = min_num(z, x, y); return z; }

if (.xorsign && !isPresent(c)) { xorsign = getSignBit(a) ^ getSignBit(b); } if (.abs) { a = |a|; b = |b|; if (isPresent(c)) { c = |c|; } }

d = two_inputs_min(d, a, b) if (isPresent(c)) { d = two_inputs_min(d, d, c) } if (.xorsign && !isPresent(c) && !isNaN(d)) { setSignBit(d, xorsign); }

9.7.3.12. Floating Point Instructions: max

def max_nan (z, x, y) { if (isNaN(x) || isNaN(y)) z = NaN; else // note: +0.0 > -0.0 here z = (x > y) ? x : y; return z; }

def two_inputs_max (z, x, y) { if (.NaN) z = max_nan(z, x, y); else z = max_num(z, x, y); return z; }

if (.xorsign && !isPresent(c)) { xorsign = getSignBit(a) ^ getSignBit(b); } if (.abs) { a = |a|; b = |b|; if (isPresent(c)) { c = |c|; } }

d = two_inputs_max (d, a, b) if (isPresent(c)) { d = two_inputs_max (d, d, c) }

if (.xorsign && !isPresent(c) !isNaN(d)) { setSignBit(d, xorsign); }

9.7.3.13. Floating Point Instructions: rcp

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.14. Floating Point Instructions: rcp.approx.ftz.f64

9.7.3.15. Floating Point Instructions: sqrt

.rnd = { .rn, .rz, .rm, .rp };

9.7.3.16. Floating Point Instructions: rsqrt

9.7.3.17. Floating Point Instructions: rsqrt.approx.ftz.f64

9.7.3.18. Floating Point Instructions: sin

9.7.3.19. Floating Point Instructions: cos

9.7.3.20. Floating Point Instructions: lg2

9.7.3.21. Floating Point Instructions: ex2

9.7.3.22. Floating Point Instructions: tanh

9.7.4. Half Precision Floating-Point Instructions

9.7.4.1. Half Precision Floating Point Instructions: add

add{.rnd}.bf16 d, a, b; add{.rnd}.bf16x2 d, a, b;

.rnd = { .rn };

ld.global.b32 f3, [addr + 8]; // load 32 bit which hold packed bf16x2 ld.global.b32 f4, [addr + 12]; // load 32 bit which hold packed bf16x2 add.bf16x2 f5, f3, f4; // SIMD bf16x2 addition

9.7.4.2. Half Precision Floating Point Instructions: sub

sub{.rnd}.bf16 d, a, b; sub{.rnd}.bf16x2 d, a, b;

.rnd = { .rn };

9.7.4.3. Half Precision Floating Point Instructions: mul

mul{.rnd}.bf16 d, a, b; mul{.rnd}.bf16x2 d, a, b;

.rnd = { .rn };

9.7.4.4. Half Precision Floating Point Instructions: fma

.rnd = { .rn };

// scalar bf16 fused multiply-add fma.rn.bf16 d1, a1, b1, c1; fma.rn.relu.bf16 d1, a1, b1, c1; fma.rn.oob.bf16 d1, a1, b1, c1; fma.rn.oob.relu.bf16 d1, a1, b1, c1;

9.7.4.5. Half Precision Floating Point Instructions: neg

9.7.4.6. Half Precision Floating Point Instructions: abs

9.7.4.7. Half Precision Floating Point Instructions: min

9.7.4.8. Half Precision Floating Point Instructions: max

9.7.4.9. Half Precision Floating Point Instructions: tanh

.type = {.f16, .f16x2, .bf16, .bf16x2}

9.7.4.10. Half Precision Floating Point Instructions: ex2

.atype = { .f16, .f16x2} .btype = { .bf16, .bf16x2}

9.7.5. Mixed Precision Floating-Point Instructions

9.7.5.1. Mixed Precision Floating Point Instructions: add

add{.rnd}.dtype2.atype2.ctype2 d, a, c; add.rz.ftz.dtype3.atype3.ctype2 d, a, c; add.rz.dtype4.atype3.ctype2 d, a, c;

.atype = { .f16, .bf16 }; .cdtype = { .f32 }; .atype2 = { .f16x2, .bf16x2 }; .dtype2 = .ctype2 = .atype3 = { .f32x2 }; .dtype3 = { .f16x2 }; .dtype4 = { .bf16x2 }; .rnd = { .rn, .rz, .rm, .rp };

9.7.5.2. Mixed Precision Floating Point Instructions: sub

.atype = { .f16, .bf16 }; .rnd = { .rn, .rz, .rm, .rp }; .cdtype = { .f32 }; .atype2 = { .f16x2, .bf16x2 }; .dtype2 = .ctype2 = .atype3 = { .f32x2 }; .dtype3 = { .f16x2 }; .dtype4 = { .bf16x2 };

9.7.5.3. Mixed Precision Floating Point Instructions: fma

.abtype = { .f16, .bf16 }; .cdtype = { .f32 }; .atype = { .f16x2, .bf16x2 }; .btype = .ctype = .dtype = { .f32x2 }; .rnd = { .rn, .rz, .rm, .rp };

9.7.5.4. Mixed Precision Floating Point Instructions: mul

.dtype1 = { .f16x2 } .dtype2 = { .bf16x2 } .atype1 = .ctype1 = { .f32x2 } .dtype3 = .atype2 = { .bf16x2 } .ctype2 = { .f16x2 } .dtype4 = .atype3 = { .f16x2 } .ctype3 = { .bf16x2 }

9.7.6. Alternate Floating-Point Instructions

9.7.6.1. Alternate Floating Point Instructions: add

.cdtype = { .e5m2x4, .e4m3x4 }; .atype = { .e5m2x4, .e4m3x4, .e3m2x4, .e2m3x4, .e2m1x4, .e2m1p4x4, .ue8m0x4 }; .rnd = { .rn };

iC[0] = c[0:7]; iC[1] = c[8:15]; iC[2] = c[16:23]; iC[3] = c[24:31];

for (i = 0; i < 4; i++) { d[i] = iA[i] + iC[i]; }

// f8x4 addition mov.b32 ra, {ba0, ba1, ba2, ba3}; // pack four f8 as f8x4 mov.b32 rc, {bc0, bc1, bc2, bc3}; // pack four f8 as f8x4 add.rn.e5m2x4.e4m3x4.satfinite rd, ra, rc; // SIMD addition

9.7.6.2. Alternate Floating Point Instructions: sub

.cdtype = { .e5m2x4, .e4m3x4 }; .atype = { .e5m2x4, .e4m3x4, .e3m2x4, .e2m3x4, .e2m1x4, .e2m1p4x4, .ue8m0x4 }; .rnd = { .rn };

iC[0] = c[0:7]; iC[1] = c[8:15]; iC[2] = c[16:23]; iC[3] = c[24:31];

for (i = 0; i < 4; i++) { d[i] = iA[i] - iC[i]; }

// subtraction of f8x4 from ue8m0x4 mov.b32 ra, {ba0, ba1, ba2, ba3}; // pack four ue8m0 values mov.b32 rc, {bc0, bc1, bc2, bc3}; // pack four f8 as f8x4 sub.rn.e5m2x4.ue8m0x4.satfinite rd, ra, rc;

9.7.6.3. Alternate Floating Point Instructions: mul

.dtype = { .e5m2x4, .e4m3x4 }; .atype = .ctype = { .e5m2x4, .e4m3x4, .e3m2x4, .e2m3x4, .e2m1x4, .e2m1p4x4, .ue8m0x4 }; .rnd = { .rn };

for (i = 0; i < 4; i++) { d[i] = iA[i] * iC[i]; }

9.7.6.4. Alternate Floating Point Instructions: fma

.cdtype = { .e5m2x4, .e4m3x4 }; .atype = .btype = { .e5m2x4, .e4m3x4, .e3m2x4, .e2m3x4, .e2m1x4, .e2m1p4x4, .ue8m0x4 }; .rnd = { .rn };

iC[0] = c[0:7]; iC[1] = c[8:15]; iC[2] = c[16:23]; iC[3] = c[24:31];

for (i = 0; i < 4; i++) { d[i] = iA[i] * iB[i] + iC[i]; }

9.7.7. Comparison and Selection Instructions

9.7.7.1. Comparison and Selection Instructions: set

set.CmpOp.type d, a, b;

.CmpOp = { eq, ne, lt, le, gt, ge, lo, ls, hi, hs}; .type = { .u8x4, .s8x4, .u16x2, .s16x2 };

9.7.7.2. Comparison and Selection Instructions: setp

.CmpOp = { eq, ne, lt, le, gt, ge, lo, ls, hi, hs, equ, neu, ltu, leu, gtu, geu, num, nan }; .BoolOp = { and, or, xor }; .type = { .b16, .b32, .b64, .u16, .u32, .u64, .s16, .s32, .s64, .f32, .f64 };

9.7.7.3. Comparison and Selection Instructions: selp

.type = { .b16, .b32, .b64, .u16, .u32, .u64, .s16, .s32, .s64, .f32, .f64 };

9.7.7.4. Comparison and Selection Instructions: slct

.dtype = { .b16, .b32, .b64, .u16, .u32, .u64, .s16, .s32, .s64, .f32, .f64 };

9.7.8. Half Precision Comparison Instructions

9.7.8.1. Half Precision Comparison Instructions: set

set.CmpOp.bf16.stype d, a, b; set.CmpOp.BoolOp.bf16.stype d, a, b, {!}c;

set.CmpOp{.ftz}.dtype.f16 d, a, b; set.CmpOp.BoolOp{.ftz}.dtype.f16 d, a, b, {!}c; .dtype = { .u16, .s16, .u32, .s32}

set.CmpOp.dtype.bf16 d, a, b; set.CmpOp.BoolOp.dtype.bf16 d, a, b, {!}c; .dtype = { .u16, .s16, .u32, .s32}

set.CmpOp{.ftz}.dtype.f16x2 d, a, b; set.CmpOp.BoolOp{.ftz}.dtype.f16x2 d, a, b, {!}c; .dtype = { .f16x2, .u32, .s32}

set.CmpOp.dtype.bf16x2 d, a, b; set.CmpOp.BoolOp.dtype.bf16x2 d, a, b, {!}c; .dtype = { .bf16x2, .u32, .s32}

.CmpOp = { eq, ne, lt, le, gt, ge, equ, neu, ltu, leu, gtu, geu, num, nan }; .BoolOp = { and, or, xor }; .stype = { .b16, .b32, .b64, .u16, .u32, .u64, .s16, .s32, .s64, .f16, .f32, .f64};

9.7.8.2. Half Precision Comparison Instructions: setp

setp.CmpOp{.ftz}.f16x2 p|q, a, b; setp.CmpOp.BoolOp{.ftz}.f16x2 p|q, a, b, {!}c;

setp.CmpOp.bf16 p, a, b; setp.CmpOp.BoolOp.bf16 p, a, b, {!}c;

setp.CmpOp.bf16x2 p|q, a, b; setp.CmpOp.BoolOp.bf16x2 p|q, a, b, {!}c;

.CmpOp = { eq, ne, lt, le, gt, ge, equ, neu, ltu, leu, gtu, geu, num, nan }; .BoolOp = { and, or, xor };

setp.gt.or.bf16x2 u|v,c,d,s; @q setp.eq.bf16 u,j,m;

9.7.9. Logic and Shift Instructions

9.7.9.1. Logic and Shift Instructions: and

.type = { .pred, .b16, .b32, .b64 };

9.7.9.2. Logic and Shift Instructions: or

.type = { .pred, .b16, .b32, .b64 };

9.7.9.3. Logic and Shift Instructions: xor

.type = { .pred, .b16, .b32, .b64 };

9.7.9.4. Logic and Shift Instructions: not

.type = { .pred, .b16, .b32, .b64 };

9.7.9.5. Logic and Shift Instructions: cnot

.type = { .b16, .b32, .b64 };

9.7.9.6. Logic and Shift Instructions: lop3

.BoolOp = { .or , .and };

immLut = F(ta, tb, tc);

If F = (a | b | c); immLut = 0xF0 | 0xCC | 0xAA = 0xFE

If F = (a & b & ~c); immLut = 0xF0 & 0xCC & (~0xAA) = 0x40

If F = ((a & b | c) ^ a); immLut = (0xF0 & 0xCC | 0xAA) ^ 0xF0 = 0x1A

9.7.9.7. Logic and Shift Instructions: shf

.mode = { .clamp, .wrap };

// 128-bit left shift; n < 32 // [r7,r6,r5,r4] = [r3,r2,r1,r0] << n shf.l.clamp.b32 r7,r2,r3,n; shf.l.clamp.b32 r6,r1,r2,n; shf.l.clamp.b32 r5,r0,r1,n; shl.b32 r4,r0,n;

shf.r.clamp.b32 r1,r0,r0,n; // rotate right by n; n < 32 shf.l.clamp.b32 r1,r0,r0,n; // rotate left by n; n < 32

// extract 32-bits from [r1,r0] starting at position n < 32 shf.r.clamp.b32 r0,r0,r1,n;

9.7.9.8. Logic and Shift Instructions: shl

.type = { .b16, .b32, .b64 };

9.7.9.9. Logic and Shift Instructions: shr

.type = { .b16, .b32, .b64, .u16, .u32, .u64, .s16, .s32, .s64 };

9.7.10. Data Movement and Conversion Instructions

9.7.10.1. Cache Operators

9.7.10.2. Cache Eviction Priority Hints

9.7.10.3. Data Movement and Conversion Instructions: mov

.type = { .pred, .b16, .b32, .b64, .u16, .u32, .u64, .s16, .s32, .s64, .f32, .f64 };

9.7.10.4. Data Movement and Conversion Instructions: mov

.type = { .b16, .b32, .b64, .b128 };

// unpack 8-bit elements from .b16 { d.x, d.y } = { a[0..7], a[8..15] } // unpack 8-bit elements from .b32 { d.x, d.y, d.z, d.w } { a[0..7], a[8..15], a[16..23], a[24..31] }

// unpack 16-bit elements from .b32 { d.x, d.y } = { a[0..15], a[16..31] } // unpack 16-bit elements from .b64 { d.x, d.y, d.z, d.w } = { a[0..15], a[16..31], a[32..47], a[48..63] }

// unpack 32-bit elements from .b64 { d.x, d.y } = { a[0..31], a[32..63] }

// unpack 32-bit elements from .b128 { d.x, d.y, d.z, d.w } = { a[0..31], a[32..63], a[64..95], a[96..127] } // unpack 64-bit elements from .b128 { d.x, d.y } = { a[0..63], a[64..127] }

9.7.10.5. Data Movement and Conversion Instructions: shfl (deprecated)

.mode = { .up, .down, .bfly, .idx };

// Warp-level INCLUSIVE PLUS REVERSE-SCAN:
//
// Assumes input in following registers:
//     - Rx  = sequence value for this thread
//
shfl.down.b32  Ry|p, Rx, 0x1,  0x1f;

// BUTTERFLY REDUCTION:
//
// Assumes input in following registers:
//     - Rx  = sequence value for this thread
//
shfl.bfly.b32  Ry, Rx, 0x10, 0x1f;   // no predicate dest
add.f32        Rx, Ry, Rx;
shfl.bfly.b32  Ry, Rx, 0x8,  0x1f;
add.f32        Rx, Ry, Rx;
shfl.bfly.b32  Ry, Rx, 0x4,  0x1f;
add.f32        Rx, Ry, Rx;
shfl.bfly.b32  Ry, Rx, 0x2,  0x1f;
add.f32        Rx, Ry, Rx;
shfl.bfly.b32  Ry, Rx, 0x1,  0x1f;
add.f32        Rx, Ry, Rx;
//
// All threads now hold sum in Rx

9.7.10.6. Data Movement and Conversion Instructions: shfl.sync

.mode = { .up, .down, .bfly, .idx };

lane[4:0] = [Thread].laneid; // position of thread in warp bval[4:0] = b[4:0]; // source lane or lane offset (0..31) cval[4:0] = c[4:0]; // clamp value segmask[4:0] = c[12:8];

// get value of source register a if thread is active and // guard predicate true, else unpredictable if (isActive(Thread) && isGuardPredicateTrue(Thread)) { SourceA[lane] = a; } else { // Value of SourceA[lane] is unpredictable for // inactive/predicated-off threads in warp } maxLane = (lane[4:0] & segmask[4:0]) | (cval[4:0] & ~segmask[4:0]); minLane = (lane[4:0] & segmask[4:0]);

switch (.mode) { case .up: j = lane - bval; pval = (j >= maxLane); break; case .down: j = lane + bval; pval = (j <= maxLane); break; case .bfly: j = lane ^ bval; pval = (j <= maxLane); break; case .idx: j = minLane | (bval[4:0] & ~segmask[4:0]); pval = (j <= maxLane); break; } if (!pval) j = lane; // copy from own lane d = SourceA[j]; // copy input a from lane j if (dest predicate selected) p = pval;

9.7.10.7. Data Movement and Conversion Instructions: prmt

.mode = { .f4e, .b4e, .rc8, .ecl, .ecr, .rc16 };

if ( ! mode ) { ctl[0] = (c >> 0) & 0xf; ctl[1] = (c >> 4) & 0xf; ctl[2] = (c >> 8) & 0xf; ctl[3] = (c >> 12) & 0xf; } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3; }

tmp[07:00] = ReadByte( mode, ctl[0], tmp64 ); tmp[15:08] = ReadByte( mode, ctl[1], tmp64 ); tmp[23:16] = ReadByte( mode, ctl[2], tmp64 ); tmp[31:24] = ReadByte( mode, ctl[3], tmp64 );

9.7.10.8. Data Movement and Conversion Instructions: ld

ld{.weak}{.ss}{.level1::eviction_priority}{.level2::eviction_priority}{.level::cache_hint}{.level::prefetch_size}{.vec}.type d, [a]{.unified}{, cache_policy};

ld.volatile{.ss}{.level::prefetch_size}{.vec}.type d, [a];

ld.relaxed.scope{.ss}{.level1::eviction_priority}{.level2::eviction_priority}{.level::cache_hint}{.level::prefetch_size}{.vec}.type d, [a]{, cache_policy};

ld.acquire.scope{.ss}{.level1::eviction_priority}{.level2::eviction_priority}{.level::cache_hint}{.level::prefetch_size}{.vec}.type d, [a]{, cache_policy};

ld.mmio.sem.sys{.global}.type d, [a];

ld{.ss}.type.proxy::readonly d, [a];

ld.global.b16 %r,[fs]; // load .f16 data into 32-bit reg cvt.f32.f16 %r,%r; // up-convert f16 data to f32

ld.global.f32 d,[ugbl].unified; ld.b32 %r0, [%r1].unified;

ld.global.L1::evict_last.u32 d, [p];

ld.global.L2::64B.b32 %r0, [gbl]; // Prefetch 64B to L2 ld.L2::128B.f64 %r1, [gbl]; // Prefetch 128B to L2 ld.global.L2::256B.f64 %r2, [gbl]; // Prefetch 256B to L2

createpolicy.fractional.L2::evict_last.L2::evict_unchanged.b64 cache_policy, 1.0; ld.global.L2::cache_hint.b64 x, [p], cache_policy; ld.param::entry.b32 %rp1, [kparam1];

ld.global.b128 %r0, [gbl]; // 128-bit load

ld.global.acquire.mmio.sys.u32 %r0, [gbl];

// 256-bit load ld.global.L2::evict_last.v8.f32 { %reg0, _, %reg2, %reg3, %reg4, %reg5, %reg6, %reg7}, [addr]; ld.global.L2::evict_last.L1::evict_last.v4.u64 { %reg0, %reg1, %reg2, %reg3}, [addr];

ld.global.u32.proxy::readonly %r0, [%rd0]; ld.u32.proxy::readonly %r1, [%rd1];

9.7.10.9. Data Movement and Conversion Instructions: ld.global.nc

createpolicy.fractional.L2::evict_last.b64 cache_policy, 0.5; ld.global.nc.L2::cache_hint.f32 d, [a], cache_policy;

ld.global.nc.L2::64B.b32 d, [a]; // Prefetch 64B to L2 ld.global.nc.L2::256B.f64 d, [a]; // Prefetch 256B to L2

ld.global.nc.b128 d, [a];

ld.global.nc.L2::evict_first.v4.f64 {%reg0, %reg1. %reg2, %reg3}. [a]; // 256-bit load

9.7.10.10. Data Movement and Conversion Instructions: ldu

.ss = { .global }; // state space .vec = { .v2, .v4 }; .type = { .b8, .b16, .b32, .b64, .b128, .u8, .u16, .u32, .u64, .s8, .s16, .s32, .s64, .f32, .f64 };

9.7.10.11. Data Movement and Conversion Instructions: st

st.global.L1::no_allocate.f32 [p], a;

createpolicy.fractional.L2::evict_last.b64 cache_policy, 0.25; st.global.L2::cache_hint.b32 [a], b, cache_policy;

st.param::func.b64 [param1], %rp1;

st.global.b128 [a], b; // 128-bit store

st.global.release.mmio.sys.u32 [gbl], %r0;

// 256-bit store st.global.L2::evict_last.v8.f32 [addr], { %reg0, _, %reg2, %reg3, %reg4, %reg5, %reg6, %reg7};

9.7.10.12. Data Movement and Conversion Instructions: st.async

.ss = { .shared::cluster }; .type = { .b32, .b64, .b128, .u32, .u64, .s32, .s64, .f32, .f64 }; .vec = { .v2, .v4 }; .completion_mechanism = { .mbarrier::complete_tx::bytes };

st.async{.mmio}.sem.scope{.ss}.type [a], b;

.sem = { .release }; .scope = { .gpu, .sys }; .ss = { .global }; .type = { .b8, .b16, .b32, .b64, .u8, .u16, .u32, .u64, .s8, .s16, .s32, .s64, .f32, .f64 };

st.async.sys.release.global.u32 [addr], b;

st.async.mbarrier::complete_tx::bytes.b128 [addr], b, [mbar_addr];

st.async.shared::cluster.mbarrier::complete_tx::bytes.b128 [addr], b, [mbar_addr];

9.7.10.13. Data Movement and Conversion Instructions: multimem.st.async

.sem = { .release }; .scope = { .gpu, .sys }; .ss = { .global }; .type = { .b8, .b16, .b32, .b64, .u8, .u16, .u32, .u64, .s8, .s16, .s32, .s64, .f32, .f64 };

// Release store, system scope, generic addressing for multimem operand. multimem.st.async.release.sys.f64 [mm_addr], src_f64;

9.7.10.14. Data Movement and Conversion Instructions: st.bulk

st.bulk [gdst], 4096, 0;

9.7.10.15. Data Movement and Conversion Instructions: multimem.ld_reduce , multimem.st , multimem.red

multimem.ld_reduce{.ldsem}{.scope}{.ss}.op.type d, [a]; multimem.ld_reduce.weak{.ss}.op.type d, [a];

multimem.st{.stsem}{.scope}{.ss}.type [a], b; multimem.st.weak{.ss}.type [a], b;

multimem.red{.redsem}{.scope}{.ss}.op.type [a], b;

// Floating point type:

multimem.ld_reduce{.ldsem}{.scope}{.ss}.op{.acc_prec}{.vec}.type d, [a]; multimem.ld_reduce.weak{.ss}.op{.acc_prec}{.vec}.type d, [a];

multimem.st{.stsem}{.scope}{.ss}{.vec}.type [a], b; multimem.st.weak{.ss}{.vec}.type [a], b;

multimem.red{.redsem}{.scope}{.ss}.redop{.vec}.redtype [a], b;

multimem.st.relaxed.gpu.b32 [addr3], val3_b32; multimem.st.release.cta.global.u32 [addr4], val4_u32;

multimem.red.relaxed.gpu.max.f64 [addr5], val5_f64; multimem.red.release.cta.global.add.v4.f32 [addr6], {val6, val7, val8, val9}; multimem.ld_reduce.add.acc::f32.v2.f16x2 {val_10, val_11}, [addr7];

9.7.10.16. Data Movement and Conversion Instructions: prefetch , prefetchu

prefetchu.L1 [a]; // prefetch to uniform cache

prefetch{.tensormap_space}.tensormap [a]; // prefetch the tensormap

.space = { .global, .local }; .level = { .L1, .L2 }; .level::prefetch_size = { .L1::32B }; .level::eviction_priority = { .L2::evict_last, .L2::evict_normal }; .tensormap_space = { .const, .param };

9.7.10.17. Data Movement and Conversion Instructions: applypriority

.level::eviction_priority = { .L2::evict_normal };

9.7.10.18. Data Movement and Conversion Instructions: applypriority.async.bulk

.level::eviction_priority = { .L2::evict_normal }; .src = { .global }; .completion_mechanism = { .bulk_group };

9.7.10.19. Data Movement and Conversion Instructions: applypriority.async.bulk.tensor

9.7.10.20. Data Movement and Conversion Instructions: discard

.level = { .L2 };

9.7.10.21. Data Movement and Conversion Instructions: createpolicy

// Fabric range-based policy createpolicy.range.fabric.level::primary_priority{.level::secondary_priority}.b64 cache_policy, [aLe, aOff], primary-size, total-size;

// Fraction-based policy createpolicy.fractional.level::primary_priority{.level::secondary_priority}.b64 cache_policy{, fraction};

// Converting the access property from CUDA APIs createpolicy.cvt.L2.b64 cache_policy, access-property;

.level::primary_priority = { .L2::evict_last, .L2::evict_normal, .L2::evict_first, .L2::evict_unchanged }; .level::secondary_priority = { .L2::evict_first, .L2::evict_unchanged };

createpolicy.range.L2::evict_last.L2::evict_first.b64 policy, [ptr], 0x100000, 0x200000;

createpolicy.range.fabric.L2::evict_last.L2::evict_first.b64 policy, [leid, off], 0x100000, 0x200000;

// access-prop is created by CUDA APIs. createpolicy.cvt.L2.b64 policy, access-prop;

9.7.10.22. Data Movement and Conversion Instructions: isspacep

.space = { const, .global, .local, .shared{::cta, ::cluster}, .param{::entry} };

9.7.10.23. Data Movement and Conversion Instructions: cvta

// convert generic address to const, global, local, or shared address cvta.to.space.size p, a;

.space = { .const, .global, .local, .shared{::cta, ::cluster}, .param{::entry} }; .size = { .u32, .u64 };

9.7.10.24. Data Movement and Conversion Instructions: cvt